單元認知測試（CAT）方法利用明確定位單元內部的缺陷以有效的提升檢測製程中缺陷的能力。在傳統的CAT中，通常以電阻值為0Ω模擬單元中的短路行為，以及一個極高的電阻值模擬單元中的斷路行為。在本篇論文中，我們提出在CAT中模擬不同的電阻值以提升針對電路中測試仍能影響電路行為的最小缺陷的能力。電路行為模擬結過將被有效的儲存在臨界電阻值矩陣(CRM)中，此一矩陣不僅明確指出測試向量能否檢測各缺陷，還包含了此缺陷能被檢測到的電阻臨界值，並在後續的流程中指引ATPG選擇晶片的測試向量。為了評估一組測試向量對於電路中最小缺陷的檢測能力，我們提出了一個新的專用指標：最弱缺陷的失效涵蓋率(WFC)。本篇論文的實驗在現行的商用ATPG工具上實現此一方法。由於CAT具有彈性的流程，使用者可以利用任何現已發行的EDA工具重複執行此實驗。實驗結果顯示我們提出的方法能有效降低WFC的遺漏率，與傳統CAT的結果比較，在實驗的12個電路設計中降低約12.5%。此結果顯示，本文中的方法能確實提升測試向量對於電路難測缺陷的敏感度，與此同時，原始的失效涵蓋率(FC)仍能保持原本的數值。

Cell-aware test (CAT) has been shown to significantly improve manufacturing test quality by explicitly targeting cell-internal short and open defects. CAT library cell characterization is typically done for two resistor values: 0Ω for hard shorts and one extremely high value for hard opens. In this thesis, we propose a cell-aware test generation approach that explicitly targets the weakest still-detectable defect variant for each identified cell-internal defect location. A critical resistance matrix (CRM) is introduced to efficiently store the characterization results and guide ATPG tools to select the chip patterns. We formulate a dedicated metric for this objective: the weakest-defect fault coverage (WFC). The novel approach is implemented in an experimental scripted ATPG tool flow, using commercial tools as building blocks. Due to the flexibility of CAT flow, user could build this tool flow using only standard-release tools that anyone can reproduce the experiment. Compared to regular CAT, experimental results show that our approach reduces WFC escapes with up to 12.5% and thus significantly enhances the test’s sensitivity for weak defects, while maintaining the original (hard defect) fault coverage (FC).

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