單晶片系統中所擁有的核心數量隨著半導體科技的發展而快速增加，在應用方面存取資料的比例也越來越高，晶片中各個模組的溝通逐漸成為整體效能的瓶頸。
晶片上網路架構(NoC)是解決這類溝通問題的一種有效方法，一些商業應用如Alteris FlexNoC可以產生出由數種組件組合而成的網路。

由於晶片網路對效能的影響甚鉅，有許多研究提出不同的電子系統層級的時間模型來進行效能、面積、耗能等各方面的評估以及縮短設計的時程。在這類的模型中，準確度和模擬速度的取捨往往是關鍵。

在這篇論文中，我們以Flit Propagation Model為基礎，提出我們的時間模型。我們的時間模型可以支援像FlexNoC這類由組件組成的網路，包括規則以及不規則的架構。我們的模型都有與硬體做時間的比對，確保每個週期的行為都是相同的。另外我們也提出了一個針對設計空間作探索的流程，包括根據需求建立網路架構以及使用時間模型進行最佳化。

我們以一個實際的例子作為實驗的目標。以我們的時間模型進行最佳化後，讀取延遲可以降低到未進行最佳化時的43.6\%，同時只使用88.1\%的面積。

On-chip interconnect has become the performance bottleneck as the number of cores and modules in a chip are increasing, particularly in data-intensive applications. In the modern System-on-Chip (SoC), the Network-on-Chip (NoC) is used to solve this problem.
Several commercial approaches such as Alteris FlexNoC provides on-chip networks constructed from primitive building blocks, based on packet-based communication protocol.

The interconnect design has a significant impact on the performance, area, and power consumption. Recently, many Electronic System-Level (ESL) timing models have been proposed to explore the design space with the constrained time-to-market. The accuracy and simulation speed are the trade-off in ESL simulation.

In this thesis, we extend the concept of flit propagation model and present a timing model of flit transactions for primitive components in irregular packet-based interconnect fabrics. Based on the
model, we then develop a fast timing simulator for on-chip
interconnects with a 100\% cycle accuracy when validated with
an industrial RTL implementation. We also propose a design space exploration flow to generate a partial-crossbar-based interconnect from the connection graph. With our timing simulator, we can evaluate and optimize the architectures of interconnects by
adjusting topologies, FIFOs, outstanding buffers, data widths,
and clocking.

In a case of high-performance networking SoC,
the proposed approach can explore the design space effectively,
minimizing the latency of intercommunication to 43.6\% as
compared with the initial architecture. The area cost can also
be reduced to 88.1\% at the same time.
With the different bandwidth requirement, the interconnect architecture can be optimized accordingly. The exploration result shows the trade-off between performance and area can be made easily with our timing model of on-chip-interconnect.

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