隨著晶片製造的演進，將許多核心放在同一塊晶片上，因為晶片製造成本昂貴，因此會依賴執行驅動全系統模擬的模擬器。隨著系統複雜，在設計參數時候會花費相當多的時間。如果只針對某個系統元件做模擬，其他元件使用較快的軌跡模擬來節省模擬時間。為了增加傳統軌跡模擬的精準度，目前有許多前人的研究是使用軌跡之間的相依性讓元件的回應時間可以視模擬器的反應。在這篇論文，我們實作了相依性的想法在Gem5的晶片網路模擬器上，並且討論遇到的問題以及如何去解決。實驗結果發現相依性感知的軌跡模擬精準度在3.22%，而原本的結果錯誤率是14.97%。

With the vast advances in chip manufacturing, it is now common to pack many processor cores onto a single chip. Efficient architectural designs of such multicore systems often rely on execution-driven, full-system simulators, such as Gem5. However, as the complexity of the system architectures rises, exploiting the design space is becoming very time-consuming. On the other hand, if the architectural design focuses on specific system components, such as Network-on-Chip (NoC) or memory hierarchy, trace-driven simulations offer an alterna-tive for fast design space exploitation. To enhance the fidelity of traditional trace-based simulators, recent works advocate the use of dependences between trace events to allow the responses of the target component be accounted for in calculating the simulated time. In this thesis, we apply the idea to the NoC simulator of Gem5, Garnet, and discuss how to make Garnet dependency-aware. It turns out that this effort is quite involved and many is-sues have to be resolved. We discuss these issues and show our considerations and solutions. The resultant dependency-aware trace-driven NoC simulator is evaluated by comparing its performance outputs against those from Gem5. Based on our evaluations, the dependency-aware Garnet can keep the performance differences within 3.22%, while the original Garnet may result in errors as high as 14.97%

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