現代混合尺寸電路通常包含數百萬個元件，其中只有少數是巨集元件。
過去已經有各種電路擺置演算法被發明來優化設計目標，其中電線長度的
最小化是關鍵的一環。電線長度最小化的研究主要集中在尋找巨集元件和
標準單元元件的最佳位置，和探索翻轉方向的處理方法。然而，在有關擺
置問題的文獻中，與電線長度優化相關的巨集元件翻轉問題相對較少受到
關注。
在這項研究中，我們探索了在兩階段擺置流程中用於巨集元件翻轉方
向的優化技術。兩階段擺置流程面臨的主要挑戰在於巨集元件和標準單元
元件之間的差距。為了解決這一挑戰，我們提出了兩種巨集元件的翻轉技
術，有助於彌合這一差距。第一種技術在簡化的且基於梯度的分析標準單
元元件擺置器內實現。第二種技術可用於任意的黑盒擺置器來獲得初始擺
置，從中求得巨集元件的翻轉方向。
通過實驗，我們證明當與著名的學術擺置器NTUplace3 結合使用時，
這兩種技術與一個單純的向內翻轉啟發式方法相比，能夠實現更短的電線
長度。這些發現強調了巨集元件翻轉在電線長度優化中的重要性，充實了
現有巨集元件和標準單元元件擺置演算法的研究。

Modern mixed-size circuits typically consist of millions of blocks,
with only a few of them being macros. Various placement algorithms
have been proposed to optimize design objectives, among which wire
length minimization plays a crucial role. The study of wire length minimization primarily focuses on finding optimal positions for macros
and standard cells, while also exploring orientation handling methods.
However, the problem of macro flipping, which contributes to wire
length optimization, has received relatively less attention in the placement literature.
In this work, we investigate the refinement of flipping orientations
for macros in a two-stage placement flow. A major challenge in two stage placement flows lies in the gap between the placement of macros
and standard cells. To address this challenge, we propose two macro
flipping techniques that help bridge this gap. The first technique is designed to be implemented within a simplified gradient-based analytical standard cell placer. The second technique relies on an arbitrary black box placer to obtain an initial placement, from which we determine the macro flipping orientations.
Through experimentation, we demonstrate that when coupled with
the well-known academic placer NTUplace3, both techniques achieve
shorter wire lengths compared to a simple inward-flipping heuristic.
These findings underscore the significance of macro flipping in wire
length optimization, complementing existing research on macro and
standard cell placement algorithms.

[1] T.-C. H. H.-C. C. Y.-W. C. Tung-Chieh Chen, Zhe-Wei Jiang, “NTUplace3: An analytical placer for large-scale mixed-size designs with preplaced blocks and density constraints,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 27, pp. 1228–1240, Jul 2008.
[2] M.-K. Hsu and Y.-W. Chang, “Unified analytical global placement for large scale mixed-size circuit designs,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 31, pp. 1366–1378, Sep 2012.
[3] Y.-W. C. F.-J. H. Tung-Chieh Chen, Ping-Hung Yuh and D. Liu, “MP-trees: a packing-based macro placement algorithm for mixed-size designs,” IEEE TCAD, vol. 27, pp. 1621–1634, Sep 2008.
[4] Y.-W. C. Chin-Hao Chang and T.-C. Chen, “A novel damped-wave framework for macro placement,” Proc. ICCAD, pp. 504–511, Nov 2017.
[5] S.-T. C. Y.-W. C. Chien-Hsiung Chiou, Chin-Hao Chang, “Circular-contour based obstacle-aware macro placement,” Proc. of ASP-DAC, pp. 172–177, Jan 2016.
[6] Y.-W. C. Hsin-Chen Chen, Yi-Lin Chuang and Y.-C. Chang, “Constraint graph-based macro placement for modern mixed-size circuit designs,” Proc. ICCAD, pp. 218–223, Sep 2008.
[7] C.-H. C. Y.-W. C. C.-J. W. Yi-Fang Chen, Chau-Chin Huang, “Routability driven blockage-aware macro placement,” Proc. of DAC, pp. 1–6, Jun 2014.
[8] Personal communication.
[9] N. V. J. Z. Yan and C. Chu, “An effective floorplan-guided placement algorithm for large-scale mixed-size designs,” ACM Transactions on Design Automation of Electronic Systems, vol. 19, pp. 1–25, Jun 2014.
[10] J. P.-M. G.-O. Alex Vidal-Obiols, Jordi Cortadella and F. Martorell, “Multilevel dataflow-driven macro placement guided by rtl structure and analytical methods,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 40, pp. 2542–2555, Dec 2021.
[11] K. S. Tony Chan, Jason Cong, “Multilevel generalized force-directed method for circuit placement,” Proceedings of the 2005 international symposium on Physical design, pp. 185–192, Apr 2005.