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研究生: 張悅
Chang, Yueh
論文名稱: 適用於橢圓曲線密碼之二元域節能架構
Energy Efficient Architecture for Elliptic Curve Cryptography over Binary Fields
指導教授: 黃稚存
Huang, Chih-Tsun
口試委員: 馬席彬
黃俊達
張錫嘉
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 資訊工程學系
Computer Science
論文出版年: 2011
畢業學年度: 100
語文別: 英文
論文頁數: 49
中文關鍵詞: 橢圓曲線硬體架構無線射頻辨識系統
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  • 近年來,橢圓曲線密碼系統受到學界和業界的高度重視,許多世界上知名國際標準和國家標準機構也已經採納此系統,現在生活中也出現許多相關的重要應用,例如:橢圓曲線數位簽章(ECDSA)。與另一個公開金鑰密碼系統RSA比較起來,橢圓曲線密碼系統可以使用長度較短的公鑰與私鑰達到相同的安全等級。因此,橢圓曲線密碼系統更加適合用於功率消耗較低的裝置,例如:RFID。
    在本文中,提出一個適用於橢圓曲線密碼系統的節能硬體架構。我們首先選擇適合的設計參數,例如:質數有限體的選擇,演算法的選擇和運算元件的設計。接著,我們利用化簡運算元件的多工器結構降低面積,根據不同的結構提出不同的運算排程。最後,我們分析,修改運算排程,使得硬體架構更趨於平衡,藉此降低面積與能量消耗。使用TSMC 65奈米CMOS 製程進行合成,此架構實作上需要17 K邏輯閘,進行一個163位元的橢圓曲線密碼運算需要花費250毫秒,消耗 1.4 u焦耳的能量,與其他的設計比較的結果可以看出此硬體架構在能量消耗是最低的。


    Elliptic Curve Cryptography (ECC) has become popular for security system. In this work, we propose an operation scheduling and corresponding EC engine for scalar multiplication. Proposed Arithmetic Unit (AU) consists of 1 high-radix multiplier, 1 bit-parallel squarer, and 2 adders. In order to reduce area, we combine the multiplier, squarer and adder to eliminate AU input multiplexers. Parameter selection helps for reducing cycle and area. We use Montgomery Ladder Algorithm to avoid power analysis resistance. A bit-parallel squarer is implemented to reduce cycle. The experiments show the balanced implementations consume lower energy. Clock gating technology is applied for reducing power consumption.
    Using TSMC 65nm CMOS technology, our EC engine could implement a scalar multiplication in 250ms at 95KHz over GF(2163). According to the synthesis result, EC engine features smaller area (17Kgates), low power consumption (5.5uW) and low energy consumption (1.4uJ). The energy comparison between our work and other published literatures shows that our approach is the best.

    1 Introduction 1 1.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.3 Previous Works . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.4 Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.5 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 Mathematical Background 5 2.1 Elliptic Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2 Scalar Multiplication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.3 Binary Field Arithmetic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3 Hardware Implementation 15 3.1 Parameter Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.2 Proposed EC engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.3 Proposed Arithmetic Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.4 Multiplier Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.5 Squarer Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4 Operation Scheduling 28 4.1 Original Scheduling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.2 The Improved Schedule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.3 State machine of EC engine . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5 Experiment Result 37 5.1 Implementation Result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5.2 Comparison with Related Works . . . . . . . . . . . . . . . . . . . . . . . . . 41 6 Conclusion and Future Work 44 6.1 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

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