矽薄膜電晶體元件可撓特性之研究｜國立清華大學博碩士論文庫

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研究生：	彭逸軒 Peng,, I-Hsuan
論文名稱：	矽薄膜電晶體元件可撓特性之研究 Investigation of Flexibility of Silicon Thin Film Transistors
指導教授：	吳泰伯 Wu, Tai-Bor 劉柏村 Liu, Po-Tsun
口試委員:
學位類別：	博士 Doctor
系所名稱：	工學院 - 材料科學工程學系 Materials Science and Engineering
論文出版年：	2009
畢業學年度：	97
語文別：	英文
論文頁數：	109
中文關鍵詞：	撓曲性、金屬基板、直接沉積多晶矽薄膜
外文關鍵詞：	flexible, metal foil substrate, directly deposition microcrystalline silicon films
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本研究主題為低溫複晶矽薄膜電晶體在不□鋼基板上，撓曲多次前後元件特性及可靠度之探討。不同撓曲程度對元件電性上的影響，並且配合變溫量測和不同通道長度量測萃取源/汲極寄生電阻和缺陷密度來分析去除寄生電阻後載子遷移率的特性變化並且探討原因。個別在不同撓曲情況下，P型複晶矽薄膜電晶體在直流電壓操作下，實驗結果發現在撓曲的情況下，不論是張應力或壓應力起始電壓偏移均較平面情況下為嚴重，然而壓應力下經由長時間直流電壓操作後，載子遷移率較張應力下長時間直流電壓操作為佳，也顯示壓應力下對於元件的可靠度較張應力下更優。
附件研究主題為以Inductively coupled plasma chemical vapor deposition (ICP-CVD)系統中於低溫成長奈米多晶矽薄膜之研究，在低基板溫度150℃下，以約5.33 nm/s 的鍍膜速度成功成長出結晶程度91.35%的奈米多晶矽薄膜。以ICP-CVD在150℃可直接在玻璃基板上，成長出高品質 n+ 摻雜奈米多晶矽薄膜(n+ nc-Si:H)無須預先沉積孕核層。以拉曼光譜(Raman spectra)計算n+ nc-Si:H結晶性可高達85%以上，晶粒大小約20奈米，薄膜片電阻低於103 Ω/sq，電阻係數約為 2.7 Ω•cm。於低成本可撓曲基板的應用，直接沉積低溫n+ nc-Si:H之研究值得探討。

We investigated the mechanism after hundreds of bending parallel to the channel length on p-type poly silicon TFTs on metal foil substrate to discuss the device electronic characteristics and reliability. The extraction of the parasitic resistance、flat band voltage and trap density、threshold voltage、subthreshold slope and mobility were studied in detail for the mobility and current changing under bending condition. The reliability study of p-type polycrystalline silicon thin film transistors on metal foil fabricated by the ELC method under bending condition was investigated. The DC stress was utilized to simulate the operation of P-type poly-Si TFTs and to observe the degradation degree under bending condition. The result indicated threshold voltage shifted more badly in bending situation no matter under compressive or tensile condition than in plan situation. This phenomenon indicated the mobility under compressive strain with DC bias stress was better than tensile strain with DC bias stress.
High quality films of n+ microcrystalline-Si:H was directly deposited on glass substrates at 150°C by ICP-CVD without any post-deposition re-crystallization. The crystallinity of n+ nc-Si:H evaluated from Raman spectra is about 91.35% and the grain size is about 20nm with growth rate about 5.33 nm/s. Sheet resistance values of lower than 103 Ω/sq were obtained and the resistivity was about 2.7 Ω•cm. The direct deposition of n+ nc-Si:H at low temperature may deserve more and more attention according to the cost down issue and ability for flexible substrate usage.

Abstract(Chinese) ...................................................................................................................... I
Abstract(English) ...................................................................................................................... II
Acknowledgement ................................................................................................................... IV
Content ..................................................................................................................................... V
Figure Captions ..................................................................................................................... VII
Table Captions .......................................................................................................................... X

Chapter 1 Introduction: .........................................................................................................1
Chapter 2 Literature review: ..................................................................................................9
2-1. Stability of the thin-film transistors ....................……………………………………..11
2-2. Review of studies on poly-TFT under DC stress……… ....................................…….13
Chapter 3 LTPS on metal foil substrate: … ....................................................................…17
3-1. Introduction......................... ……… .................................….......................................17
3-2. Experimental procedures……… ..................................................................................21
3-2-1. Fabrication process of poly-Si on metal foil .........................................................21
3-2-2. Methods of Device Parameter Extraction .............................................................24
3-2-2-1. Determination of the Threshold Voltage (Vth) ..............................................24
3-2-2-2. Determination of the Subthreshold Swing (S.S) ............................................24
3-2-2-3. Determination of the field-effect mobility μFE ..............................................24
3-2-2-4. Determination of the trap density Nt ..............................................................26
3-2-2-5. Determination of the parasitic series resistance Rpa .......................................28
3-2-2-6. Determination of the strain of the surface ......................................................29
3-2-3 Experiment Procedures of P-type poly-Si on metal foil ........................................30
3-2-3-1. Bending performance of p-type poly-Si on metal foil ...................................30
3-2-3-2. Electronic property variation under bending Status .......................................31
3-2-3-3. DC stress under bending status. .....................................................................31
3-3. Result and discussion……………………………………………................................32
3-3-1. Bending Performance of P-type Poly-Si on Metal Foil………………………….32
3-3-2. Density of States and trap density Extraction……………………………………33
3-3-3. The TFTs Charaterization under Mechanical Strain……………..…………...…34
3-3-3-1. Electrical Property Variation under Different Bending Status……………...34
3-3-3-2. Analysis of Activation Energy and trap density Extraction………………...35
3-3-3-3. Analysis of Parasitical Series Resistance Extraction……………………….37
3-3-4. Reliability Analysis of poly-Si TFT under Bending Condition………….……...41
3-3-4-1. Gate DC Bias Stress Reliability Investigations…………………………….41
3-3-4-2. Comparison of Electrical Property under Different Condition………….….42
Chapter 4 Conclusions: … ……………………………………………………………..…69
References…………………………………………………………………………….……...71
Apendix Directly deposition of microcrystalline Silicon by ICD-CVD: … ...................….76
A. Introduction......................... ……… ....................................….......................................76
B. Literature review................... ……… ..................................….......................................77
i.Directly depostion of nanocrycryslline Silincon ...........................................................77
ii. Description of the HVCVD .........................................................................................79
iii. Stability of the nc-Si:H TFTs .....................................................................................80
iv. Modelling of nc-Si:H TFTs ........................................................................................81
C. Experimental procedures……… .....................................................................................82
i. Fabrication of nc-Si:H TFTs ………………..………..................................................82
ii. Simplified sample................. …………………..………............................................84
iii. Channel passivation(CHP) sample…………………………..……….......................85
iv. Process parameters………………………………….………..……….......................85
C. Result and discussion……………………………..……………….................................88
i. Electrical characterisation of the nc-Si:H TFTs............................................................88
ii. Stability of the nc-Si:H TFTs.......................................................................................91
Appendix reference: .............................................................................................................106

                                

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