隨著連結數目與晶片之間較短電訊路徑的需求逐漸增加，新興
的技術必須克服傳統封裝與效能的限制。近年來，三維整合技術(3D Integration)被廣泛的研究，晶片或晶圓堆疊結構配合直通矽晶穿孔技術(Through Slicon Via, TSV)由於可提供垂直連結路徑以及多功能的特性，因此成為一個有效並且具有潛力的解決方案。但是雖然3D-IC/Packaging結構能夠提供高效能與異質整合的特性，但是散
熱以及熱應力將會是主要的問題。
本研究首先參考台灣工業技術研究院(Industrial Technology
Research Institute, ITRI)與日本超先端電子技術開發機構(Association of Super-Advance Electronic Technologies, ASET)的設計概念與結構，建立晶片堆疊之有限元素模型。而為了解三維晶片堆疊結構的力學問題，本研究運用有限元素模擬分析並配合參數化分析，針對製程模擬、封裝與電路板層級結構進行探討。此外根據參數化分析之結果，為了解各設計因子之間的敏感度與交互作用關係，亦利用統計實驗設計當中的因子設計法(Factorial Designs)進行敏感度分析(Analysis of Variance, ANOVA)。
而為驗證有限模擬分析方法的可行性，本研究透過杜曼-格林干涉法(Twyman-Green Interferometer)量測晶片的預翹曲，並與有限元素分析結果進行比較。而由結果顯示，本研究採用之模擬分析與真實結構的力學行為有相同的變化趨勢。
然而根據結構分析結果，導孔的直徑與晶片厚度的大小為影響此封裝結構的主要因素。最後根據本論文針對三維晶片堆疊結構的可靠度分析結果，可依循不同的設計參數歸納出相對應的設計規範，並期望此分析結果能作為後續研究之參考。

As the demands for higher interconnections and shorter electrical path between chips have increased, the emerging technologies are required to break through the limitation of conventional package technology and performance. In recent years, three-dimensional (3D) integration has been widely studied. Chip or wafer stacking combined with through silicon via (TSV) technology become an effective and potential solution due to the vertical interconnections and multi-function. Although 3D-IC/Package structure provides high performance and heterogeneous characteristics, the major problems of heat dissipations and its corresponding thermal induced stresses still remain.
In this Research, we refer to the design concept and structure of 3D IC/Packaging of Industrial Technology Research Institute (ITRI) and Association of Super-Advance Electronic Technologies (ASET) to create the baseline finite element model. In order to assess the thermal-mechanical characteristic of 3D chip stacking structure, the finite element analysis (FEA) with parametric study in process modeling, package level, and board level is carried out. Futhermore, the factorial designs with the analysis of variance (ANOVA) are conducted to obtain the sensitivity information and interaction relationship between factors of the structure.
In order to validate the fininte element analysis, Twyman-Green Interferometer is used for mearsuring the pre-warpage of chips. Compare the simulations and experiments, the results indicate the finite element method can be used to describe the mechanical behaviors of real structure.
From the structure analysis in this research, the simulation results indicate that the diameter of Copper vias and thickness of chip are the major factors which influence the reliability of the 3D stacking structure the most. Based on the reliability assessment, the design windows of the chip stacking structure are established. Finally, the results of this study may provide a design guideline and a useful reference for future research.

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