研究生: |
陳佳壕 |
---|---|
論文名稱: |
SONOS快閃記憶體元件中氮化矽製程之研究 Research of Silicon Nitride layer on SONOS Flash Memory Devices |
指導教授: |
張廖貴術
Kuei-Shu Chang-Liao |
口試委員: | |
學位類別: |
碩士 Master |
系所名稱: |
原子科學院 - 工程與系統科學系 Department of Engineering and System Science |
論文出版年: | 2004 |
畢業學年度: | 92 |
語文別: | 中文 |
論文頁數: | 94 |
中文關鍵詞: | 快閃記憶體 、氮化層 |
外文關鍵詞: | ONO, SONOS, FLASH |
相關次數: | 點閱:2 下載:0 |
分享至: |
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報 |
在本論文中針對新架構的SONOS快閃記憶體元件採用不同階段的快速熱處理條件,來探討記憶體元件的初始特性及可靠度分析;首先,藉由不同的上層氧化(top oxide)層厚度來探討結構的差異對SONOS元件電特性的影響;當上層氧化層厚度較厚的元件與上層氧化層厚度較薄的元件比較時,我們可發現以下幾個特點:1.在寫入特性方面,若要讓啟始電壓飄移量較大時,需要有較薄的上層氧化(top oxide)層厚度,而在抹除方面,較薄的上層氧化(top oxide)層厚度也會在比較短的時間內抹除氮化層陷阱(trap)所陷住的電子;而在電荷保持力方面,兩者僅有些微的差距,還有在抗汲極電壓干擾方面也是以較薄的上層氧化(top oxide)層擁有較佳的特性。
本篇論文所探討的另一個特性則是在沈積底層氧化(bottom oxide)層與氮化層後所搭配的不同階段的快速熱處理,其中底層氧化(bottom oxide)層沈積後所做的處理有三項:分別是不做任何熱處理、一階段的N2O熱處理製程與做完一階段的N2O熱處理製程後再加第二階段的N2O熱處理製程。
接著在做完上述步驟後,再沈積中間的氮化層,待沈積完成後所的熱處理有三項:不做任何的熱處理、一階段的NH3熱處理製程(使用爐管)與做完一階段熱處理製程後在作第二階段的N2O熱處理製程。
經由上述實驗所得的數據,當SONOS元件的ON兩層不做任何的熱處理製程時,其讀/寫方面表現出較佳的元件特性,且擁有更快的操作速度,僅在電荷保持力的部分稍微差了點,另外在抗汲極電壓干擾的能力也較強。
還有在電荷保持力的比較上,我們發現所對氮化矽層進行氨氣(NH3)800℃ /10 min. 氮化製程的熱處理會使SONOS元件在電荷保持力上超過不做任何熱處理的元件;然而再多的熱處理製程對元件的電荷保持力增強有限,反而會使元件的記憶體特性下降。
1. White, M.H.; Adams, D.A.; Bu, J. ”On the go with SONOS”, IEEE Circuits and Devices Magazine, Volume: 16 Issue: 4, Jul 2000 Page(s): 22 -31.
2. Okayama, Y.; Kasai, K.; Yamaguchi, T.; Ooishi, A.; Takayanagi-Takagi, M.; Matsuoka, F.; Kinugawa, M. ”Nitrogen concentration optimization for down-scaled CMOSFET with
N 2O-based oxynitride process”, VLSI Technology, 1998. Digest of Technical Papers. 1998 Symposium on , 9-11 Jun 1998 Page(s): 220 -221.
3. Doyle, B.S.; Philipossian, A. ”Role of nitridation/reoxidation of NH3-nitrided gate dielectrics on the hot-carrier resistance of CMOS transistors”, IEEE Electron Device Letters, Volume: 18 Issue: 6 , Jun 1997 Page(s): 267 -269.
4. Rama I. Hegde, Bikas Maiti, Philip J. Tobin, ”Growth and Film Characteristics of N2O and NO Oxynitride Gate and Tunnel Dielectrics”, J. Electrochem. Soc, Vol.144, No.3, p.1081 (1997).
5. Lin, W.H.; Pey, K.L.; Dong, Z.; Choi, S.Y.-M.; Zhou, M.S.; Ang, T.C.; Ang, C.H.; Lau, W.S.; Ye, J.H. ”Effects of post-deposition anneal on the electrical properties of Si3N4 gate dielectric”, IEEE Electron Device Letters , Volume: 23 Issue: 3 , Mar 2002 ,Page(s): 124 -126.
6. Tam, P.K. Ko and C. Hu, ”Lucky-Electron Model of Channel Hot-Electron Injection in MOSFETs”, IEEE Trans. Electron Dev. ED-31, P.116, 1984.
7. Hankang Bu; While, M.H.; ”Retention reliability enhanced SONOS NVSM with scaled programming voltage ”,Aerospace Conference Proceedings, 2002. IEEE , Volume: 5 , 2002 Page(s): 2383 -2390.
8. Myung Kwan Cho; Kim, D.M. ”High performance SONOS memory cells free of drain turn-on and over-erase: compatibility issue with current flash technology”, IEEE Electron Device Letters , Volume: 21 Issue: 8 , Aug 2000 Page(s): 399 -401.
9. Yamada, Y. Hiwa, T. Tamane, K. Amemiya, Y. Ohshima and K. Yoshikawa, ”Degradation Mechanism of Flash EEPROM Program After Program/Erase Cycles”, International Electron Device Meeting, P.23, 1993.
10. White, M.H.; Yang Yang; Ansha Purwar; French, M.L. ”A low voltage SONOS nonvolatile semiconductor memory technology”, Components, Packaging, and Manufacturing Technology, Part A, IEEE Transactions on [see also Components, Hybrids, and Manufacturing Technology, IEEE Transactions on] , Volume: 20 Issue: 2 , Jun 1997 Page(s): 190 -195.
11. H. Nishino, N. Hayasaka, K. Horioka, J. Shiozawa, S. Nadahara, N. Shooda,Y. Akama, A. Sakai, and H. Okano. ”Smoothing of the Si surface using CF4/02 down-flow etching”, J. Appl. Phys., Vol. 74, No. 2, 15 July 1993.
12. H.-C. Tseng C. Y. Chang F. M. Pan and L. P. Chen ”Effects of dry etching damage removal on low-temperature silicon selective epitaxial growth”, J. Appl. Phys. 78 (7), 1 October 1995.
13. Tsai, W.J.; Zous, N.K.; Liu, C.J.; Liu, C.C.; Chen, C.H.; Tahui Wang; Pan, S.; Chih-Yuan Lu; Gu, S.H., ”Data retention behavior of a SONOS type two-bit storage flash memory cell”, Electron Devices Meeting, 2001. IEDM Technical Digest. International, 2001 Page(s): 32.6.1 -32.6.4.
14. F. R. Libsch and M.H. White, ”Charge transport and storage of low programming voltage SONOS/MONOS memory devices, ” Sol. St. Elect., vol.33, p.105, 1990.
15. Jiankang Bu; White, M.H. ”Effects of two-step high temperature deuterium anneals on SONOS nonvolatile memory devices”, IEEE Electron Device Letters, Volume: 22 Issue: 1 , Jan 2001 Page(s): 17 -19.
16. Tanaka, M.; Saida, S.; Mitani, Y.; Mizushima, I.; Tsunashima, Y. ”Highly reliable MONOS devices with optimized silicon nitride film having deuterium terminated charge traps”, Electron Devices Meeting, 2002. IEDM '02. Digest. International, 2002 Page(s): 237 -240.
17. ”Nonvolatile Semiconductor Memory Technology”, Edited by William D. Brown; Joe E. Brewer; IEEE Press.
18. Yamada, Y. Hiwa, T. Tamane, K. Amemiya, Y. Ohshima and K. Yoshikawa, ”Degradation Mechanism of Flash EEPROM Programming After Program/Erase Cycles”, International Electron Devices Meeting, P.23, 1993.
19. S.C. Vltkavage and E.A. Irene, ”Electrical and ellipsometric characterization of the removal of silicon surface damage and contamination resulting from ion beam and plasma processing”, J. Appl. Phys. 64(4), 15 August 1988.
20. Song, S.C.; Luan, H.F.; Lee, C.H.; Mao, A.Y.; Lee, S.J.; Gelpey, J.; Marcus, S.; Kwong, D.L. ”Ultra thin high quality stack nitride/oxide gate dielectrics prepared by in-situ rapid thermal N2O oxidation of NH3 -nitrided Si”, VLSI Technology, 1999. Digest of Technical Papers. 1999 Symposium on, 1999 Page(s): 137 -138.
21. Tsai, W.J.; Gu, S.H.; Zous, N.K.; Yeh, C.C.; Liu, C.C.; Chen, C.H.; Tahui Wang; Pan, S.; Chih-Yuan Lu; ”Cause of data retention loss in a nitride-based localized trapping storage flash memory cell ”,Reliability Physics Symposium Proceedings, 2002. 40th Annual , 2002 Page(s): 34 -38.
22. Eitan, B.; Pavan, P.; Bloom, I.; Aloni, E.; Frommer, A.; Finzi, D.; ”NROM: A novel localized trapping, 2-bit nonvolatile memory cell ”,IEEE Electron Device Letters , Volume: 21 Issue: 11 , Nov 2000 Page(s): 543 -545.
23. Sugizaki, T.; Kobayashi, M; Ishidao, M. ;Minakaca, H.; Yamaguchi, M.; Tamura, Y.; Sugiyama, Y.; Nakanishi, T.; Tanaka, H.; ”Novel multi-bit SONOS type flash memory using a high-K charge trapping layer” ,2003 IEEE Symposium on VLSI Technology Digest of Technical Papers Page(s): 24 -28
24. Min She, Hideki Takeuchi, Member, IEEE, and Tsu-Jae King, Senior Member, IEEE; ”Silicon-Nitride as a tunnel dielectric for improved SONOS-type flash memory”, IEEE Electron Device Letters , Volume: 24 NO.5 , MAY 2003 Page(s): 309 -311.
25. B. Dipert and M. Levy, “Designing with Flash memory”, Published by Annabooks, 1993.
26. S. Tam, P. K. Ko, and C. Hu, “Lucky-Electron Model of Channel Hot-Electron Injection in MOSFET’s” , IEEE Transaction on Electron Devices, Vol.31, September 1984, p.1116.
27. T. Wang, W. J. Tsai., S.H. Gu , C.T. Chan, C.C. Yeh , N.K. Zous, T.C. Lu , Sam Pan, and C.Y. Lu, “Reliability Models of Data Retention and Read-Disturb in 2-bit Nitride Storage Flash Memory Cells(Invited Paper) ”, IEEE 2003.
28. C.C. Yeh, W.J. Tsai, T.C. Lu, H.Y. Chen, H.C. Lai, N.K. Zous, Y.Y. Liao, G.D. You, S.K. Cho, C.C. Liu, F.S. Hsu, L.T. Huang, W.S. Chiang, C.J. Liu, C.F. Cheng, M.H. Chou, Tahui Wang, Wenchi Ting, Sam Pan, Joseph Ku,and Chih-Yuan Lu, “Novel Operation Schems to Improve Device Reliability in a Localized Trapping Storage SONOS-type Flash Memory ”, IEEE 2003.