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研究生: 鄭 文
Cheng, Wen
論文名稱: 基於動態規劃之量子比特映射與路由問題和交換深度優化
Dynamic Programming-Based Qubit Mapping and Routing with Swap Depth Optimization
指導教授: 何宗易
Ho, Tsung-Yi
王廷基
Wang, Ting-Chi
口試委員: 麥偉基
Mak, Wai-Kei
李淑敏
Li, Shu-Min
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 資訊工程學系
Computer Science
論文出版年: 2024
畢業學年度: 112
語文別: 中文
論文頁數: 27
中文關鍵詞: 量子電路動態規劃量子耦合保真度
外文關鍵詞: Qubit Mapping and Routing, Noisy intermediate-scale quantum (NISQ)
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  • 量子位元映射和路由(QMR)是設計量子電腦的關鍵步驟。 QMR 需要將邏輯量子位元映射到實體佈局,同時正確地路由量子位元。邏輯量子位元映射到物理佈局中,需要同時正確路由所有邏輯門。但是在此限制之下,現有的 QMR 演算法主要專注於在路由過程中減少交換閘門的數量,而忽略了由此增加的最大量子閘門數(MGCQ),這對量子電腦效能產生了重大影響。嚴重影響了電路的正確性。為了克服這個難題,我們設計了基於動態規劃的 QMR 演算法,該演算法可優化最大量子閘門數,從而提高電路正確性。我們在常用的量子電路集評估了我們的演算法性能。我們的演算法正確性超越最先進的 MaxSAT 演算法,在最佳的情況下提高了 10.17\%。


    Qubit mapping and routing (QMR) is a critical step in designing a quantum computer because
    it maps logical qubits to a physical layout while properly routing all control gates.
    However, existing QMR algorithms mainly focus on reducing the number of swap gates during the routing, ignoring the resulting Maximum Gate Count Per Qubit (MGCQ), significantly impacting the worst-case fidelity. To overcome this challenge, we introduce a dynamic programming-based QMR algorithm that optimizes the MGCQ for improved worst-case fidelity. We have evaluated the promising performance of our algorithm on a set of commonly used quantum circuit benchmarks. As an example, our algorithm can improve the worst-case fidelity of the state-of-the-art QMR algorithm, MaxSAT, by up to 10.17\%.

    Abstract (Chinese) I Abstract II Acknowledgements III Contents IV List of Figures VI List of Tables VIII 1 Introduction 1 2 BACKGROUND 6 2.1 Quantum Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.2 Qubit Mapping and Routing (QMR) . . . . . . . . . . . . . . . . . 6 2.3 Worst-Case Fidelity in QMR . . . . . . . . . . . . . . . . . . . . . . 7 3 Methodology 9 3.1 Problem Formulation . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.2 Initial Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.3 Pathfinding Technique . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.4 Qubit Routing and Placement . . . . . . . . . . . . . . . . . . . . . 13 3.5 Gate Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.6 Parallel Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.7 Accelerate Technique: Slicing . . . . . . . . . . . . . . . . . . . . . 19 4 Experimental Results 20 4.1 Baseline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.2 Overall Performance Comparison . . . . . . . . . . . . . . . . . . . 21 4.3 Parallelization Performance among the Number of Processors . . . . 22 4.3.1 Fidelity Comparison: With and Without Load Balance . . . 23 5 Conclusions 24 Bibliography 25

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