本實驗主要是以磁控濺鍍法鍍製BST/(Ta2O5)1-x(TiO2)x薄膜於高阻值矽基板(n-type，電阻率>15000Ω-cm)上，以共平面的結構進行高頻(1MHz)與微波頻段(1~25GHz)的變容特性量測，其中(Ta2O5)1-x(TiO2)x層作為high-k介電緩衝層，而緩衝層的置入一般被認為可提升整體
結構的有效介電常數，並降低微波能量在矽基板發生的損耗，進而使得此結構可以幫助鐵電薄膜與矽基板製程進行整合，藉著製程穩定性高、控制容易、技術成熟的半導體製程將薄膜型被動元件整合在單一晶片上，可滿足高頻通訊被動元件嚴格之規格要求，並藉此降低製程成本。
實驗主要是改變high-k緩衝層的薄膜特性，來觀察其對整體BSTcoplanar結構變容特性的影響，實驗結果發現，在BST/buffer/HRS結構未進行退火熱處理時，無論在高頻(1MHz)與微波頻段(1~25GHz)下皆無明顯的調變性，推究其原因為，當矽基板為undoped時(ρ>15000Ω-cm)，其表現為近中性的基板，即無法提供載子作為變容的效果，而在將BST/buffer/HRS結構進行700°C氧氣氛退火熱處理後，無論在高頻1MHz與微波頻段(1~25GHz)皆出現明顯的調變性，可解釋為當進行高溫退火處理時，中性矽基板表面形成了一層n-type Si層，因而提供了主要的調變力來源，並由於緩衝層殘留帶正電的氧空缺，形成類似正fixed oxide charge的影響，使得其串聯後的C-V圖峰值大幅提升，在高頻(1MHz)與微波(1~25GHz)下皆有顯著的調變性，而由此可證明在上述頻段中，調變力的主要來源還是n-type Si層所提供，而鐵電調變層由於水平方向電場密度太小而幾乎無貢獻於調變力。而在鍍膜條件、退火溫度、氛圍等不易避免的現象將會使得單一Metal-Oxide-Semiconductor(MOS)的平帶電壓產生偏移，使得兩個back-to-back串接而成C-V圖顯現出製程相關的結果，並反應在不同的極值電容及迥異的loss-V圖，同時也影響到微波頻段的特性。因此與矽基板緊緊相鄰的緩衝層便會對矽基板表面層載子所貢獻的變容性發生嚴重的影響，經由改變緩衝層的鍍製氣氛發現，不同的氬氧比，將會對成長於其上的BST鐵電薄膜造成些許的差異，且在高頻與微波頻段皆有不同程度的影響，而當改變緩衝層膜厚時，在高頻顯現了越厚的緩衝層將會使得調變率下降，但由於不同厚度條件差異極小，故在微波頻段時，調變率的改變不大，但略呈現先升後降，且FOM亦呈現有最佳值存在，在緩衝層厚度為50nm時，BST/(Ta2O5)0.917(TiO2)0.083/HRS結構在2.45GHz時有79.17%的調變率，FOM值為2.676，在DC bias為24V時，在25GHz下仍有45%的調變率，而FOM值為6.54，但膜厚低於50nm時，使用磁控濺鍍鍍製時，控制力不佳，不易鍍出平整的界面，而實驗結果亦顯示界面性質嚴重影響整體變容表現，故將來若能使用更高品質的方式成長厚度更薄的緩衝層，也許更能有效的控制製程條件，也更有機會將高調變性鐵電薄膜導入矽基板製程，達到有效的降低生產成本的目標，並能廣泛地運用在相關微波元件上。

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