最近幾年來，半導體產業快速的被研發與進步著，且進步的速度在這三十多年來一直被莫爾定律所支配著，一般相信在未來十年內還是會繼續遵守這個定律。而由於通道長度的縮小，為了確保閘極對通道仍有良好的控制能力而不會因短通道效應而變差，於是閘二氧化矽介電層厚度也必須相對的變薄。根據近年來的半導體產業發展藍圖，當閘通道長度縮短到0.07微米以下後，我們所需要的閘二氧化矽介電層厚度必須要小於1.5奈米，並在未來的幾年內將投入生產。這樣超薄的二氧化矽介電層厚度下，當閘極電壓操作在1伏特時，閘極漏電流將超過1A/cm2，這樣大的漏電流對許多應用尤其是邏輯電路可能是不被允許的。所以為了解決超薄閘二氧化矽介電層所帶來的問題又要保有它的好處，所以必須尋找一些新較高的介電常數介電層材料來替代傳統閘二氧化矽介電材料。但是最近幾年的研究顯示，在深次微米元件使用High-K閘介電材料時，將遭遇到由閘極到汲極或源極邊緣區域電場所引起的短通道效應。在本篇論文的研究中，提出對於閘堆疊結構且通道長度為50nm元件以下，進行以模擬為基礎的分析研究。研究中將發現一些幾何參數如閘長度、介面深度以及側壁寬度對於邊緣導致能障下降的影響。並且本論文將提出一新的閘堆疊結構，可以有效的解決使用High-K材料所導致的不理想的效應。

Recently studies have shown that by adapting high-K gate dielectric, deep sub-micron MOSFET suffers short channel effect caused by the fringing electric fields from gate to source/drain regions. In this work, a simulation-based analysis of multiple gate stack structure with channel length as short as 50nm is presented. The geometry effect such as gate length, junction depth and spacer width on fringing - induced - barrier - lowing (FIBL) is studied. The new stake gate structure can be optimized for reducing the undesirable fringing induced barrier lowing effect of high-K gate dielectric MOSFETs.

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