高介電材料於高遷移率砷化銦鎵：達到低界面陷阱態密度及高性能自動對準反轉式通道MOSFET之研發

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研究生：	邱漢欽 Chiu, Han-Chin
論文名稱：	高介電材料於高遷移率砷化銦鎵：達到低界面陷阱態密度及高性能自動對準反轉式通道MOSFET之研發 High-κ dielectrics on high carrier mobility InGaAs: achieving low interfacial density of states and high-performance self-aligned inversion-channel MOSFETs
指導教授：	洪銘輝 Hong, Minghwei 郭瑞年 Kwo, Raynien
口試委員:	鄭克勇 Cheng, K. Y. 劉致為 Liu, C. W. 郭治群 Guo, J. C. 皮敦文 Pi, P. W. 王永和 Wang, Y. H. 賴聰賢 Lay, T. S.
學位類別：	博士 Doctor
系所名稱：	工學院 - 材料科學工程學系 Materials Science and Engineering
論文出版年：	2011
畢業學年度：	99
語文別：	英文
論文頁數：	116
中文關鍵詞：	砷化鎵、砷化銦鎵、高速電子、原子層沉層、高介電、界面陷阱態密度、三五金氧半電晶體、三五族半導體製程、自動對準
外文關鍵詞：	GaAs, InGaAs, high mobility, atomic-layer-deposition (ALD), high-k, interfacial density of states, III-V MOSFET, Conductance method, Quasi-state CV, Fermi-level movement efficiency, III-V process, Self-aligned, ICP-RIE
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Atomic-layer-deposited Al2O3 on In0.53Ga0.47As with short air-exposure between the oxide and semiconductor deposition without any InGaAs surface treatments has shown negligible frequency-dispersion capacitance-voltage (CV) characteristics in the depletion and accumulation region, and well-behaved frequency-dependent inversion curves. The interfacial density of states (Dit) of the metal-oxide-semiconductor capacitor (MOSCAP) was determined by the Terman method and the conductance method. The Dit distribute over the bandgap of In0.53Ga047As in “U”-shape giving lower Dit values near the mid-gap were obtained about 5×1011-3×1012 eV-1cm-2. By the conductance method, however, the Dit values were adopted as the authentic values and the Dit close to the mid-gap is about 3×1012 eV-1cm-2. The quasi-static CV characteristics indicate a high efficiency of 63% for the Fermi-level movement efficiency near the mid-gap.
On the basis of the high quality Al2O3/InGaAs interface, self-aligned enhancement-mode (E-mode) inversion-channel InxGa1-xAs (x=0.53 and 0.75) n-MOSFETs using atomic-layer-deposited Al2O3 as the gate dielectric have been demonstrated. Devices with lower dopant activation temperature (DAT) and higher indium content channel show better output DC characteristics. A low subthreshold swing ~ 103 mV/dec was obtained from the In0.75Ga0.25As MOSFETs with DAT of 600oC; furthermore, a maximum drain current (IDS) ~ 1.1 mA/μm was measured at a drain-to-source voltage of 1 V from a 350-nm gate-length device, the highest value among all enhancement-mode inversion-channel n-MOSFETs using InGaAs as the channels and ex-situ grown high-□ dielectrics. In addition, device optimization including TiN gate metal etching by ICP-RIE, channel doping, S/D implantation, and channel engineering were also studied in this work.

Table of Contents
Publication List………………………………...……………………….I
Abstract………………………………………...………………………III
Table of Contents……………………………………………………...V
List of Figures………………………………………………………VIII
List of Tables…………………………………………………….…XIV
Chapter 1 Introduction………………………………………………..1
1.1 Background and Motivation…...……………………………………………1
1.2 Alternative channel materials…………………………………………………2
1.3 High-κ Dielectric on InGaAs……...….…………………….......................….5
1.4 High-κ/InGaAs Interface Characterization……………………………...……7
1.5 Device Structure……………………...………………………....…………….9
Chapter 2 Instrumentation and Theories……...……………………..19
2.1 Atomic Layer Deposition (ALD)……...……….…………………….…...19
2.2 Heat Treatment………………………...………...………………………....20
2.3 Inductively Coupled Plasma Reactive Ion Etching……....…….……......21
2.4 Electrical Measurement Instruments…..…………………..………....……23
2.4.1 Agilent 4284A Precision LCR Meter………...…………………….23
2.4.2 Agilent 4156C Semiconductor Parameter Analyzer....……..……...23
2.5 Basic Principle of Metal-Oxide-Semiconductor Capacitor.......................27
2.5.1 Capacitance-Voltage characteristics of a MOSCAP........................27
2.5.2 Determination of Oxide Dielectric Constant, Doping Concentration
, and Flat-Band Voltage  from a Capacitance-Voltage Curve…….…30
2.5.3 Extraction of Interfacial Density of States………….…………….32
2.5.3.1 Terman Method…….………………………………………..34
2.5.3.2 Conductance Method………………………………………..35
2.6 Transfer Length Method…………………………………………………38
Chapter 3 Achieving a Low Interfacial Density of States in Atomic Layer Deposited Al2O3 on In0.53Ga0.47As and Electrical Characterization……...………………………..…………..41
3.1 Introduction…………………………………………………….…………41
3.2 Sample Preparation……………………………………………………….42
3.3 ALD-Al2O3 Film Optimization by Heat Treatment………………........43
3.4 Process for Fabricating Al2O3/InGaAs MOS Capacitors………….......46
3.5 Electrical Characteristics…………………………………………………49
3.5.1 Low Leakage Current of 10-nm thick Atomic-Layer- Deposited
Al2O3 Film………………………………………………………….49
3.5.2 Capacitance-Voltage Characteristics………………………………50
3.5.3 Interfacial Density of States Extraction………………………….52
3.5.3.1 Terman Method……………………………………………..52
3.5.3.2 Conductance Method……………………………………....54
3.5.3.3 Quasi-Static Capacitance-Voltage Measurement and Fermi-
Level Movement Efficiency………………………………..56
3.5.3.4 Charge Pumping Method……...…………………………..61
3.5.3.5 Summary……………...………....…………………………..66
Chapter 4 Self-aligned Inversion-Channel InxGa1-xAs (x=0.53 and 0.75) MOSFETs using ALD-Al2O3 as Gate Dielectrics...70
4.1 Introduction…………………………………………………….…………70
4.2 Sample Preparation……………………………………………………….71
4.3 Self-aligned Process for Fabricating MOSFETs..……………………...71
4.3.1 Formation of Self-algined Gate – Titanium Nitride Etched by
ICP-RIE…………………………………………………………..71
4.3.2 Self-aligned Process for Fabricating MOSFETs………………73
4.4 Device Characteristics of InGaAs MOSFETs……………………….…82
4.4.1 DC and RF Characteristics In0.53Ga0.47As N-MOSFET with 10-
nm Thick ALD-Al2O3 as a Gate Dielectric……………………….82
4.4.2 Electrical Characteristics In0.53Ga0.47As N-MOSFET with 5-nm
Thick ALD-Al2O3 as a Gate Dielectric and 0.6 μm Gate Length...89
4.4.3 High Performance Self-aligned inversion-channel In0.75Ga0.25As
 N-MOSFET with 5-nm Thick ALD-Al2O3 as a Gate Dielectric…96
4.4.4 Comparison……………………………………………………...101
4.4.5 Submicron-meter gate length ALD-Al2O3/In0.75Ga0.25As
MOSFETs…………….…………………………………………103
4.5 Benchmark………………………………………………………………109
Chapter 5 Conclusion……………………………………………….115
 
List of Figures
Fig. 1-1 Scaling of actual transistor size with technology node to comply with Moore’s Law. Nodes with feature size less than 100 nm can be referred to as nanotechnology. ………………………………………………………………………1
Fig. 1-2 Normalized energy-delay product of n channel InSb and InGaAs quantum well transistors compared with that of standard silicon metal oxide semiconductor field-effect transistors. ………………………………………………………………3
Fig. 1-3 Schematic illustration of an inversion-channel (surface channel) MOSFET. .6
Fig. 1-4 Simple structure of a MOS capacitor to be commonly used to measure the electrical characteristics. ……………………………………………………………...8
Fig. 1-5 Cross-sectional view of (a) a conventional MOSFET, (b) a HEMT, and (c) a buried channel MOSFET. …………………………………………………………11
Fig. 1-6 Band diagrams corresponding to device structures of Fig. 1-5. Ec, Ev, Ei, and Ef represent conduction band, valence band, intrinsic Fermi-level, and Fermi-level of semiconductor, respectively. ……………………………………………………….12
Fig. 2-1 Schematic illustration of one-cycle ALD process. …………………………20
Fig. 2-2 Schematic illustration of ICP-RIE. …………………………………………21
Fig. 2-3 ICP-RIE system – ULVAC CE-300I. ………………………………………22
Fig. 2-4 Rectangular approximation method used by the Agilent 4156C. Note that the Area is equal to charge Q. …………………………………………………………25
Fig. 2-5 QSCV measurement sequrence. …………………………………………….26
Fig. 2-6 Ideal band bendings of a MOSCAP under a gate bias. ……………………27
Fig. 2-7 Ideal equivalent circuit for a MOSCAP at low frequency. …………………29
Fig. 2-8 Ideal CV curve of a MOSCAP. ……………………………………………..30
Fig. 2-9 Equivalent circuit for a MOSCAP with interfacial traps at low frequency. ..33
Fig. 2-10 High-frequency CV curves with and without Dit contributions, respectively…………………………………………………………………………...34
Fig. 2-11 Equivalent circuits for conductance measurement; (a) original circuit of a MOSCAP with Rit in series with Cit, (b) simplify (a) as Cp and Gp in parallel, (c) simplify (b) as Cm and Gm in parallel. ………………………………………………36
Fig. 2-12 Basic plot of Gp/ω versus ω. ………………………………………………37
Fig. 2-13 A transfer length method test pattern. ……………………………………..38
Fig. 2-14 A typical plot of total resistance (RT) versus spacing (d). ………………39
Fig. 3-1 The hysteresis CV curves of (a) as-deposited, (b) 375oC F.G. annealing, and (c) 300oC N2 annealing at 10 kHz. …………………………………………………44
Fig. 3-2 (a) Layout - 1st – Gate dots /Alignment marks (b) cross-sectional schematic view of structure after 1st mask lithography. ………………………………………47
Fig. 3-3 (a) Layout – 2nd – Ohmic metal (b) cross-sectional schematic view of structure after 2nd mask lithography. ………………………………………………48
Fig. 3-4 Gate leakage current density (J) as a function of gate electrical field (E). …50
Fig. 3-5 CV characteristics of the MOSCAP - TiN/Al2O3 (10 nm)/n-In0.53Ga0.47As  at various ac frequencies from 1k to 1M Hz. …………………………………………51
Fig. 3-6 Hysteresis curve of the MOSCAP - TiN/Al2O3 (10 nm)/n-In0.53Ga0.47As at 1 MHz. …………………………………………………………………………………51
Fig. 3-7 (a) Ideal CV vs. measured CV curves. (b) Dit (with error bars) distribution within bandgap for the TiN/Al2O3 (10 nm)/n-In0.53Ga0.47As MOSCAP. Ec and Ev represent conduction band and valence band, respectively. …………………………53
Fig. 3-8 (a) Gp/ω versus frequency (f). (b) Distribution of Dit versus energy. Note that Ef and Ec are the Fermi-level and conduction band, respectively. …………………..55
Fig. 3-9 QSCV measured with various sweep rates (50 to 1 mV/s) from inversion to accumulation. ………………………………………………………………………57
Fig. 3-10 ψs-VG relationship extracted from QSCV curve with a sweep rate of 1mV/sec. ……………………………………………………………………………..58
Fig. 3-11 FLME extraction from the ψs-VG relationship. ……………………………59
Fig. 3-12 Differential FLME of Fig.3-11. …………………………………………...60
Fig. 3-13 (a) top and (b) cross-sectional schematic view of a structure designed for the charge-pumping measurement……………………………………………………..62
Fig. 3-14 Charge pumping current (Icp) as function of gate pulse with frequency dependence. The inset shows Gp/ω versus frequency under different voltages measured by the conductance method………………………………………………64
Fig. 3-15 Profile of the volume densities of bulk traps (Nbt) in ALD-Al2O3 as a function of distance from the In0.53Ga0.47As surface…………………………………65
Fig. 3-16 Dit distribution vs energy for ALD-Al2O3/In0.53Ga0.47As derived by Terman method (red), conductance method (blue), and charge pumping method (green), respectively…………………………………………………………………………66
Fig. 4-1 Layout-1st Alignment mark + self-aligned gate of unit cell and one device..76
Fig. 4-2 Layout – 2nd Self-algined implantation of unit cell and one device. ……….77
Fig. 4-3 Layout – 3rd Source/drain contacts of unit cell and one device. ……………78
Fig. 4-4 Layout – 4th P-well Contacts of unit cell and one device. ………………….79
Fig. 4-5 Layout – 5th Pad contacts of unit cell and one device. ……………………..80
Fig. 4-6 Layout of the design for various electrical measurements. ………………81
Fig. 4-7 SEM image of a single device. ……………………………………………..81
Fig. 4-8 Device structure for a MOSFET with 10-nm thick ALD-Al2O3. ……..……82
Fig. 4-9 (a) DC IDS-VDS characteristics of a 100μm×1μm(W×Lmask) self-aligned inversion-channel ALD-Al2O3/In0.53Ga0.47As n-MOSFET. (b) log(IDS) and Gm as function of gate bias. ………………………………………………………………...84
Fig. 4-10 Linear extrapolation of IDS versus VGS curve at VDS=0.1V. ………………85
Fig. 4-11 Gate length of mask (Lmask) versus total measured resistance (Rtotal) at VGS=4V………………………………………………………………………………85
Fig. 4-12 Gate-to-source and gate-to-body leakage currents versus gate bias (Vg) of the device shown in Fig. 4-9. ………………………………………………………..86
Fig. 4-13 Plot of effective electron mobility (μeff) as a function of inversion charge density (Ninv). ………………………………………………………………………87
Fig. 4-14 (a) RF performance of a 50μm×1μm(W×Lmask) ALD-Al2O3/In0.53Ga0.47As inversion-channel n-MOSFET at VDS=2V and VGS=1.5V. (b) Frequency response as a function of gate bias at VDS =2V. ……………………………………………………88
Fig. 4-15 Device structure for an In0.53Ga0.47AsMOSFET with 5-nm thick ALD-Al2O3. ………………………………………………………………………….90
Fig. 4-16 (a) DC IDS-VDS characteristics of a 100μm×0.6μm self-aligned inversion-channel ALD-Al2O3(5nm)/In0.53Ga0.47As n-MOSFET. (b) log(IDS) and Gm as function of gate bias at VDS =4V and 0.1V, respectively. ………………………...91
Fig. 4-17 Scaling characteristics of IDS and maximum Gm versus inverse of gate lengths for inversion-channel 5nm-Al2O3/p-In0.53Ga0.47As MOSFETs. ……………..92
Fig. 4-18 Threshold voltage and subthreshold swing (S.S.) versus gates lengths for inversion-channel 5nm- Al2O3/p-In0.53Ga0.47As MOSFETs. ………………………...92
Fig. 4-19 HR-XPS spectra of O 1s, Al 2p, As 3d, and In 3d core-level of as-deposited,  650oC-RTA, and 750 oC-RTA ALD-Al2O3/In0.53Ga0.47As. ………………………....95
Fig. 4-20 HR-XPS spectra of O 2s and Ga 2p3/2 core-level spectra of as-deposited, 650oC-RTA, and 750oC-RTA ALD- Al2O3/In0.53Ga0.47As. …………………………96
Fig. 4-21 Device structure for an In0.75Ga0.25As MOSFET with 5-nm thick ALD-Al2O3 as a gate dielectric. ……………………………………………………..97
Fig. 4-22 Improvements of transfer characteristics in In0.75Ga0.25As MOSFETs with dopant activation temperatures (DATs) of 600oC and 650oC, respectively. (a) IDS-VDS curves and (b) IDS and Gm as function of gate bias bias at VDS =2V. ………………..99
Fig. 4-23 (a) DC IDS-VDS characteristics of a 50μm×1μm self-aligned inversion-channel ALD-Al2O3(6nm)/In0.75Ga0.25As n-MOSFET. (b) IDS and Gm as function of gate bias at VDS =2.5V. ………………………………………………100
Fig. 4-24 Drain current and peak transconductance versus inverse of gate-length (1/Lg) for ALD-Al2O3/p-In0.75Ga¬0.25As MOSFETs. ……………………………………….101
Fig. 4-25 (a) IDS-VGS and (b) Gm-VGS characteristics of the ALD-Al2O3(5nm)/ (In0.75Ga0.25As/)In0.53Ga0.47As nMOSFETs (LG = 8 μm) with various S/D dopant activation temperature (DAT) at VDS=50mV. ……………………………………102
Fig. 4-26 (a) IDS versus VDS as a function of VGS for ALD-Al2O3(5nm)/ In0.75Ga0.25As(5nm)/In0.53Ga0.47As n-MOSFETs with LG of 350 nm. (b) extrinsic and intrinsic transconductances (Gm) versus VGS at VDS=1V. ………………………….104
Fig. 4-27 (a) IDS versus VDS as a function of VGS for ALD-Al2O3(5nm)/ In0.75Ga0.25As(5nm)/In0.53Ga0.47As n-MOSFETs with LG of 200 nm. (b) IDS versus VGS at VDS=1.5V. ………………………………………………………………..………105
Fig. 4-28 Process flow of fabricating self-aligned inversion-channel ALD-Al2O¬3 In0.75Ga0.25As/In0.53Ga0.47As MOSFETs with LDD structure. ……………………...106
Fig. 4-29 (a) IDS versus VGS of a 500nm inversion-channel ALD-Al2O3/In0.75Ga0.25As MOSFET measured at drain voltages of 0.5 V and 1.5 V, respectively, showing a DIBL of 39mV/V. (b) IDS versus VGS between MOSFETs with and without LDD structure. ……………………………………………………………………………108

Fig. 4-30 Summary of (a) maximum IDS and (b) peak Gm of representative work on InxGa1-xAs (x≧0.53) E-mode inversion-channel nMOSFETs with ALD or MOCVD oxide as gate dielectric. Devices with gate-length shorter than 1μm are included. The number near each data point indicates the In content (x) of the InxGa1-xAs channel used in corresponding device. ……………………………………………………...111











List of Tables
Table 1-I. Physical properties of commonly used semiconductors. ………………..…4
Table 1-II. Comprehensive comparisons of different device structures. ……………14
Table 3-I. Parameters used for QSCV measurement by Agilent 4156C. …………....57
Table 4-I. Boiling points and formation enthalpies of titanium halides. ……………72
Table 4-II. Etching recipe for etching TiN by ICP-RIE. …………………………….73
Table 4-III. Self-aligned Process Flow (I) (II). …………………………..………74/75
Table 4-IV. Summary of devices with different oxide thicknesses, channel doping concentrations, implanted doses, and dopant-activation temperatures. ……………..94

                                

(Chapter 1)
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(Chapter 2)
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(Chapter 3)
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(Chapter 4)
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