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研究生: 杜浩銓
Tu, Hao-Chuan
論文名稱: 針對迅速且精確處理器模擬之指令導向方法
An Instruction-Oriented Approach for Fast and Accurate Processor Simulation
指導教授: 蔡仁松
Tsay, Ren-Song
口試委員:
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 資訊工程學系
Computer Science
論文出版年: 2010
畢業學年度: 99
語文別: 英文
論文頁數: 25
中文關鍵詞: 處理器模擬計算機結構模擬精確方法
外文關鍵詞: processor simulation, architecture simulation, accurate approach
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  • 這篇論文提出了一個指令導向方法來提升處理器模擬的速度同時維持時間的精確性。現存先進的處理器模擬方法已知能在機能模擬上達到很快的速度,但是有效率且精確的時間計算仍然是一個有挑戰性的任務。很少的提升已經被達成在不犧牲準確性的情況下提升模擬的速度。在這篇論文裡,我們提出有效率且有效的指令導向方法透過只模擬必要狀態一個指令接著一個指令地,而不是一個時脈接著一個時脈地更新所有的狀態。這個方法能運用到不同類型的處理器,其中包括超純量處理器。實驗結果顯示模擬性能比起傳統的時脈精確方法快十倍同時結果是百分之百精確。


    This paper proposes an instruction-oriented approach to improve processor simulation speed while maintaining timing accuracy. Existing advanced processor simulation approaches are known to be able to do functional simulation at very high speed, yet efficient and accurate timing calculation is still a challenging task. Little improve has been achieved in improving simulation speed without sacrificing accuracy. In this paper, we propose an efficient and effective instruction-oriented approach that simulates only necessary states instruction-by-instruction, instead of updating all states cycle-by-cycle. This approach can apply to various types of processor, including superscalar processor. The experimental result shows that the simulation performance is nearly 10 times faster than the traditional cycle-accurate approach, while the result is 100% accurate.

    1.Introduction 2.Related Work 3.The Proposed Approach for Processor Simulation 3.1.A Motivational Example 3.2.Instruction-Oriented Approach 4.The Proposed Algorithms 4.1.The Algorithm for In-order Execution Processor 4.1.1. Update the use_time of a Stage 4.1.2. Update the use_time of a Resource 4.2.Extension to Out-of-order Execution 5.Experiment 6.Conclusion

    [1]SimpleScalar Homepage: http://www.simplescalar.com
    [2]J. Zhu and D. Gajski, "A retargetable, ultra-fast instruction set simulator," in Proceedings of the conference on Design, automation and test in Europe. pp. 62-69, 1999.
    [3]M. Burtscher and I. Ganusov, "Automatic synthesis of high-speed processor simulators," in Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture. pp. 55-66, 2004.
    [4]A. Fauth et al. "Describing instructions set processors using nML," in Proceedings of the conference on Design, automation and test in Europe. pp. 503-507, 1995.
    [5]G. Hadjiyiannis et al, "ISDL: An instruction set description language for retargetability, " in Proceedings of the 34st annual Design Automation Conference. pp. 299-302, 1997.
    [6]A. Halambi et al, "EXPRESSION: A Language for Architecture Exploration through Compiler/Simulator Retargetability, " in Proceedings of the conference on Design, automation and test in Europe. pp. 485-490, 1999.
    [7]W. Qin et al, "Flexible and Formal Modeling of Microprocessors with Application to Retargetable Simulation," in Proceedings of the conference on Design, automation and test in Europe. pp. 556-561. 2002.
    [8]S. Pees, A. Hoffmann, V. Zivojnovic, and H. Meyr, "LISA – machine description language for cycle-accurate models of programmable DSP architectures," in Proceedings of the 36st annual Design Automation Conference. pp. 933–938, 1999.
    [9]R. Razouk, "The use of Petri Nets for modeling pipelined processors," in Proceedings of the 25st annual Design Automation Conference. pp. 548-553, 1988.
    [10]M. Reshadi , Nikil Dutt, "Generic Pipelined Processor Modeling and High Performance Cycle-Accurate Simulator Generation, " in Proceedings of the conference on Design, automation and test in Europe. pp. 786-791, 2005.
    [11]OpenRISC, available on: http://www.opencores.org/openrisc

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