在積體電路研究上，懸浮閘元件經常被用來製作非揮發性記憶體，如EPROM、快閃記憶體等。由於懸浮閘元件可相容於標準CMOS製程中，因此有許多研究將其做為設計類比電路時的一種方法。近年來，隨著製程技術的日益精進，懸浮閘元件製作上遇到許多的限制與困難。本論文針對一個可於0.18μm單層多晶矽CMOS製程中製作的懸浮閘元件進行研究開發，並將其實際應用於類比電路的設計。
本論文所製做的0.18μm懸浮閘元件，採用離子化熱電子注入做為寫入機制，FN 穿隧效應做為抹除機制。量測並討論其在不同偏壓下的寫入與抹除的操作特性，文中也提出元件耐久度與資料保久度等可靠度測試數據與推算。而為了能夠以SPICE模擬懸浮閘元件在電路操作時的特性，本論文也透過熱電子注入電流與FN穿隧電流模型的建立，提出此元件的等效電路模型，並驗證此模型的近似效果。
接著，針對Translinear電路在標準CMOS製程中製作的諸多限制，提出一個新的懸浮閘元件Translinear 電路設計方案，藉由改變電晶體的電壓電流轉換關係，減小Translinear電路在操作時的誤差；並以電流公式的推導與電路量測結果，驗證此方案的可行性。
最後，論文進一步將懸浮閘元件用於數位類比轉換器電路(DAC)的設計，透過類比記憶體電路自動對於懸浮閘進行電流寫入，並將懸浮閘電晶體所儲存的電流做為數位類比轉換器的電流源，此種設計方法可直接降低傳統DAC設計上元件不匹配的影響。另外一個優點為在實現二元權重電流數位類比轉換器時，當電流需要以2的N次方增加時，電流源電晶體(即懸浮閘記憶單元)仍只需要相同的尺寸即可，這將可大大的降低數位類比轉換器的面積。同樣以電路量測結果，驗證此設計並針對量測晶片時所碰到的問題進行討論與改進。

Floating-gate device has been widely used in many commercial nonvolatile memorie products, such as EPROM, EEPROM, flash memory, etc. Due to its good compatibility with standard CMOS process, floating gate device has been treated in some studies as an analog circuit element in the analog circuit design since the 90's. As the technology moves into deep-submicron processes, more attention needs to be paid to utilize floating gate device as an analog element.
This study proposes a floating gate device constructed with three P-channel MOSFETs fabricated in a single poly 0.18μm CMOS process. The device is programmed by ion impact hot electron, and erased by FN tunneling. Experimental data of electrical characteristics during programming and erasing, device endurance, and data retention is given in this study. In order to simulate the characteristics of the floating device by SPICE in circuit design, this study build up a SPICE compatible effective circuit model of the floating gate device, by building up the hot electron injection current model and the FN tunneling current model. Experimental data is compared with simulation results to verify the accuracy of this effective circuit model.
This study concludes with two novel application circuits of the floating gate device. To deal with many restrictions of traditional translinear circuits in standard CMOS process, this study proposes to utilize floating device as a solution. By modifying the current-voltage relationship of the transistor, reduction of errors from the translinear circuit are expected. Experimental data of the proposed circuit is given in this study to verify the new solution of translinear circuit design.
Finally, this study presents a novel design for a DAC using floating-gate MOS transistors. This approach takes the classical scaled transistor DAC techniques, where we scale our transistors by programming each transistor’s floating-gate charge instead of W/L ratios. The programming eliminates device mismatch issues on DAC performance, and greatly reduces its size. Experimental data of the proposed circuit is also given in this study.

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