研究生: |
林立穎 Lin, Lee-Ying |
---|---|
論文名稱: |
應用於生醫植入式系統之0.18μm互補式金氧半製程中高壓神經刺激電路開發 A High-Voltage Neuron Stimulator in 0.18μm CMOS Process for Biomedical Implantable Device |
指導教授: |
鄭桂忠
Tang, Kea-Tiong |
口試委員: | |
學位類別: |
碩士 Master |
系所名稱: |
電機資訊學院 - 電機工程學系 Department of Electrical Engineering |
論文出版年: | 2010 |
畢業學年度: | 98 |
語文別: | 中文 |
論文頁數: | 81 |
中文關鍵詞: | 神經刺激電路 、高電壓裝置 、生醫植入式裝置 、摺疊電壓 、浮動電壓 |
外文關鍵詞: | neuron stimulator, high-voltage driver, biomedical implantable device, voltage clothing, folding-voltage technique |
相關次數: | 點閱:3 下載:0 |
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近幾年來,生醫電子已經越來越受到大家的注意以及重視,許多研究報告顯示,生醫電子可以用來治療許多已知的疾病,並且改善病人的生活品質,因此,有許多研究開始討論如何製作植入式生醫系統,然而要設計一個植入式生醫系統必頇面臨許多挑戰,其中一些必要的條件是安全、小體積和低功耗,現今,隨著科技進步,融合離散電路的生醫晶片正符合植入式生醫系統的要求,也因此受到廣泛的研究討論。對於生醫晶片而言,很重要的一部分是神經電刺激系統,神經電刺激系統可經由充放電的機制,用來模擬並觸發神經細胞的動作電位,如此一來即可建構出電子系統與生物體本身的溝通橋樑,將電子信號轉換成生物體能接收的神經訊號,藉以輔助或者取代生物體本身喪失功能的部分。 本論文所主要研究的內容即是關於神經刺激電路的設計,一個好的神經刺激電路,必頇能輸出高對稱性的Bi-Phase波形,以及精準的控制刺激電流的強度與持續時間,還要考慮到維持電荷的平衡。隨著製程技術的演進,基於新製程能提供較高的電路集成密度,能降低製造成本,以及節省耗能的原則下,會希望使用新的製程技術取代舊有的,然而,由於生物體本身神經細胞的差異性較大,並且擁有高阻抗的輸出阻值,加上電流需要量大的緣故,導致儘管利用新製程技術,降低了功耗,免不了還是要整合高電流輸出的高壓神經刺激電路,因此,本論文即是針對高電壓的神經刺激電路做進一步的探討及研究,並提出了「浮動電壓」以及「折疊電壓」兩項創新的思考方向,並設計高壓感測電路,配合控制摺疊電壓的參考電位,如此一來可將低功耗的數位控制電路以及需要高壓環境的刺激電路整合在一塊,達成ASIC的概念,本論文最後利用TSMC 0.18μm 1P6M CMOS製程技術,將想法轉化為實際電路,製造出晶片並加以驗證,再依據量測結果與模擬比對之後並加以探討,其中特別針對高壓操作環境下,高壓對於晶片本身的影響破壞做分析討論,最後對本次的晶片設計提出改良意見,以提供後續研究做為參考資料。
Bio-medical implantable devices have drawn more and more attention in recent years. Extensive studies in neuroscience prove that neural stimulation techniques may cure or at least improve some diseases caused by neural abnormal discharge or disability. However, two of the major challenges of implantable devices are combining a high-voltage driver and low-voltage digital control in a single chip, and accommodating large voltages in smaller feature size technology. This thesis presents a new stimulator circuit structure to address these problems, using a novel voltage clothing design to reduce the voltage supply from 20V to 12V. A new folding-voltage technique solves the reliability issue. The proposed design has been fabricated with TSMC 0.18μm 1P6M CMOS technology.
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