傳統相機在拍攝過後，成像的景深以及焦點都無法再改變。但隨著光場技術的發明與進步，人們現在可以透過拍攝多張不同視角的照片後，藉由電腦運算重新調整對焦深度與光圈大小，這項被稱為數位重對焦的技術在近幾年得到科技公司的重視。舉例來說現在的智慧型手機上已經開始配置更多的鏡頭，來提供消費者更強大的攝像功能。多鏡頭手機其中一個重要的功能，就是能讓使用者用拍出單眼相機大光圈的景深效果，數位重對焦就是其中一種實現淺景深效果的方式。然而現在多鏡頭手機上的淺景深功能並非數位重對焦的結果，它無法自由對焦在所有深度，只能將前景背景分離後，針對背景做虛化模糊。過去黃朝宗等人曾提出快速的對焦演算法，它能提供物理擬真的數位重對焦影像。然而有關於這個演算法的硬體架構設計並沒有被討論過。在這篇論文中我們將會針對該演算法中計算最繁重的視點內插，探討如何將其實現到數位晶片之中。

在數位重對焦的演算法中，我們必須使用高度平行化的視點內插引擎。然而在以往的做法中並沒有考慮多組視點內插引擎平行時會遇到的問題。例如龐大的電路內部記憶體消耗，以及吞吐量無法隨著硬體數量線性上升等等。為了解決此問題，本篇論文探討了不同層面的平行方式，並且提出了行平行與視點平行的硬體設計方法來節省記憶體使用量以及突破吞吐量的限制。透過行平行的架構我們節省了70\%的記憶體面積並且增加了8\%的吞吐量。接著再透過視點平行的架構能將整體的吞吐量最高提高至7.5G pixel/second。

在這篇論文的最後我們提供了兩個設計範例：單視點合成引擎以及多視點合成引擎。我們使用台積電四零奈米半導體製程進行合成，單視點合成引擎使用了300萬個邏輯閘以及2.25KB的晶片內記憶體。多視點合成引擎則使用了1600萬個邏輯閘以及3KB的晶片內記憶體。當運作在200MHz的頻率下時，他們分別可以提供2.0G以及6.7G pixel/sec的吞吐量。而功耗的部份我們透過動態功耗分析工具(PrimeTime)在TT-corner進行估計，結果分別是32.5mW以及75.7mW。

Conventional cameras cannot alter the aperture size and focus depth after the pictures were taken. With the invention and progress made in the light field technology, people now can change the aperture size and focus depth on computers afterwards. This technique called digital refocusing is now attracting much attention than ever before. For instance, smartphones nowadays are putting more cameras to enhance the picture quality and to provide more fancy effects. Simulating the shallow depth of field effect created by conventional cameras with big aperture is one of them. However, current solutions are not digital refocusing algorithm. They create this shallow depth of field effect by blurring the background region. Huang et al. proposed a fast digital refocusing algorithm which can provide photorealistic results. However the VLSI architecture of this algorithm hasn't be discussed. In this thesis, we focus on implementing the most time-consuming part of this algorithm---view synthesis---into ASIC.

The refocusing algorithm need a highly paralleled view synthesis engine to render a great amount of pixels. Li-Ren Huang designed a VLSI architecture which can compute multiple pixels in parallel. Nevertheless, he did not consider the potential problems for further parallelism, e.g. multiple engines working simultaneously. The pixel throughput cannot grow linearly with the increase of hardware resources. And the huge on-chip memory usage is also a problem. In this thesis, we discuss different levels of view synthesis parallelism, and we propose two new VLSI design methodologies: line-level and view-level parallelism. With line-level parallelism, we save 70\% on-chip memories and increase 8\% throughput of rendered pixels. We further boost the throughput up to 7.5G pixel/sec after incorporating the view-level parallelism architecture.

Two design examples called single-view renderer and multi-view renderer are given in this thesis. They are both synthesized under TSMC 40nm technology process. Single-view renderer cost 0.3M gates and 2 kbytes on-chip memories. Multi-View renderer cost 1.6M gates and 3 kbytes on-chip memories. They can provide 2.0G and 6.7G pixel/sec throughput when operating at 200MHz. The power is measured using dynamic power analysis tool at TT-corner, 200MHz. And the results are 32.5mW and 75.7mW respectively.

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