National Tsing Hua University has proposed a platform-based three-dimensional integrated circuit (3D IC) design methodology, called Chipsburger, to reduce overall design-plus-manufacture cost. However, the overall cost would be still suboptimal if the floorplans of the platform part are designed only for a specific application. Therefore, we need to make the floorplans of the platform part suitable for multiple applications. Moreover, in 3D IC design, the inter-tier connections are realized using TSVs and we should take TSVs into consideration during floorplanning process. We propose a platform-based 3D IC floorplanner with TSV consideration. It adds TSV blocks according to the inter-tier connections and then plan them together with general blocks. The floorplans of all tiers for all applications are generated simultaneously to make the floorplans of the platform part suitable for multiple applications and minimize both total area and total wirelength under a fixed-outline constraint. Experimental results show that our algorithm indeed finds the 3D floorplans whose platform part is more suitable for multiple applications and total cost is minimized under a fixed-outline constraint.

國立清華大學已提出一個以平台為基礎的三維積體電路設計方法來減少整體設計與製造的成本，並把它稱為Chipsburger。然而如果屬於平台部分的平面規劃只是為特定的應用而設計，那整個成本可能會仍然低於理想。因此我們必須要讓屬於平台部分的平面規劃能夠適合於多個應用。此外，在三維積體電路設計中，層與層之間的連接是用矽穿孔技術來實現。在做平面規劃時，我們應該要把矽穿孔納入考量。
我們提出一個以平台為基礎並且考慮矽穿孔的三維積體電路平面規劃。它根據層與層之間的連接情況來加入矽穿孔區塊，然後與一般區塊一起做規劃。所有應用的各層平面被同時地規劃，使得屬於平台部分的平面適合於多個應用，並且在固定外形的限制下，使得總面積與總線長減到最小。實驗結果顯示，我們的演算法確實能找到平台部分更適用於多個應用的三維平面規劃，並且整個成本在固定外形的限制下最小。

[1] Y.-J. Lee, Y. J. Kim, G. Huang, M. Bakir, Y. Joshi, A. Fedorov, and S. K. Lim, “Co-design of signal, power, and thermal distribution networks for 3d ics,” in Proceedings of the Conference on Design, Automation and Test in Europe, pp. 610–615, 2009.
[2] S. Kirkpatrick, C. D. Gelatt, and M. P. Vecchi, “Optimization by Simulated Annealing,” Science, pp. 671–680, 1983.
[3] L. Cheng, L. Deng, and M. D. Wong, “Floorplanning for 3-D VLSI Design,” in Proceedings of Asia and South Pacific Design Automation Conference, pp. 405–411, 2005.
[4] Y. Ma, X. Hong, S. Dong, and C. K. Cheng, “3D CBL: An Efficient Algorithm for General 3-Dimensional Packing Problems,” in Proceedings of Midwest Symposium on Circuits and Systems, pp. 1079–1082, 2005.
[5] P. H. Shiu and S. K. Lim, “Multi-layer Floorplanning for Reliable System-on-Package,” in Proceedings of International Symposium on Circuits and Systems, pp. V-69–V-72, 2004.
[6] J. Cong, J. Wei, and Y. Zhang, “A Thermal-Driven Floorplanning Algorithm for 3D ICs,” in Proceedings of IEEE/ACM International Conference on Computer-Aided Design, pp. 306–313, 2004.
[7] Z. Li, X. Hong, Q. Zhou, Y. Cai, J. Bian, H. H. Yang, V. Pitchumani, and C.-K. Cheng, “Hierarchical 3-D Floorplanning Algorithm for Wirelength Optimization,” IEEE Transactions on Circuits and Systems, pp. 2637–2646, 2006.
[8] Y. Deng and W. P. Maly, “Interconnect Characteristics of 2.5-D System Integration Scheme,” in Proceedings of International Symposium on Physical Design, pp. 171–175, 2001.
[9] J. Cong and Y. Zhang, “Thermal Via Planning for 3-D ICs,” in Proceedings of IEEE/ACM International Conference on Computer-Aided Design, pp. 745–752, 2005.
[10] J. Li and H. Miyashita, “Post-placement Thermal Via Planning for 3D Integrated Circuit,” in Proceedings of Asia Pacific Conference on Circuits and Systems, pp. 808–811, 2006.
[11] Z. Li, X. Hong, Q. Zhou, S. Zeng, J. Bian, W. Yu, H. H. Yang, V. Pitchumani, and C.-K. Cheng, “Efficient Thermal via Planning Approach and Its Application in 3-D Floorplanning,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 645–658, 2007.
[12] X. Li, Y. Ma, X. Hong, S. Dong, and J. Cong, “LP based white space redistribution for thermal via planning and performance optimization in 3D ICs,” in Proceedings of Asia and South Pacific Design Automation Conference, pp. 209–212, 2008.
[13] J. Lu, S. Chen, and T. Yoshimura, “Performance Maximized Interlayer Via Planning for 3D ICs,” in Proceeding of International Conference on ASIC, pp. 1096–1099, 2007.
[14] X. He, S. Dong, Y. Ma, and X. Hong, “Simultaneous Buffer and Interlayer Via Planning for 3D Floorplanning,” in Proceeding of International Symposium on Quality of Electronic Design, pp. 740–745, 2009.
[15] C. M. Hung, “A Cost Model for Chipsburger - a Platform-Based 3D IC Design,” Master’s thesis, National Tsing Hua University, Hsinchu, Taiwan, 2009.
[16] H. Murata, K. Fujiyoshi, S. Nakatake, and Y. Kajitani, “VLSI Module Placement Based on Rectangle-Packing by the Sequence-Pair,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 1518–1524, 1996.
[17] X. Tang, R. Tian, and D. Wong, “Fast Evaluation of Sequence Pair in Block Placement by Longest Common Subsequence Computation,” in Proceedings of the Conference on Design, Automation and Test in Europe, pp. 106–111, 2000.
[18] S. N. Adya and I. L. Markov, “Fixed-outline Floorplanning: Enabling Hierarchical Design,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp. 1120–1135, 2003.
[19] Parquet [Online] Available
http://vlsicad.eecs.umich.edu/BK/parquet/
[20] GSRC Benchmarks [Online]
http://www.gigascale.org/