具功率意識之元件庫應用:序向邏輯電路設計｜國立清華大學博碩士論文庫

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研究生：	孫瑞彣 Ruei-Wun Sun
論文名稱：	具功率意識之元件庫應用:序向邏輯電路設計 Cell Library for Power-Aware Applications: Sequential Circuit Design
指導教授：	馬席彬 Hsi-Pin Ma
口試委員:
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2008
畢業學年度：	96
語文別：	英文
論文頁數：	79
中文關鍵詞：	標準元件庫、低功耗、低電壓、特徵化
外文關鍵詞：	Standard cell library, Low power, Low supply voltage, Characterization
相關次數：	點閱：2 下載：0
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隨著先進製成技術的演進, 在現代電路設計中特別著重於低功率跟高效能為設計目標。其中在數位電路設計部份, 邏輯標準單位設計流程為最常被使用的方式去履行完成晶片設計,然而在標準單位設計流程中, 標準元件庫扮演重要角色。在不同元件庫中標準邏輯元件庫為
主要組成大部分數位電路的元件庫。對於數位電路設計者而言, 使用低功率元件庫來設計電路為簡單快速方法, 來達到低功耗目標。在標準元件庫中有一些被使用的低功耗技術, 其中最有效率減少功率消耗的方法就是降低電路操作電壓。

為了發展合適的低操作電壓的標準元件庫, 標準邏輯元件需要在低操作電壓下特別設計考量。而在這篇碩士論文中著重於在低電壓下標準元件的序向電路計。序向元件電路主要功能在於隨著不同時序控制與重置訊號來進行資料儲存與清除, 然而這也造成序向電路消耗大量動態功率消耗。因此在低電壓條件下的序向電路研究勢必需要的。此外元件庫特徵化流程也需要特別的設置針對低操作電壓應用。在低操作電壓的影響, 標準元件庫的約束限制也變得更加嚴謹。

為了低功耗跟高效能目的, 低電壓標準元件庫的最佳應用在於具有不同操作電壓的電路設計。使用一般標準元件庫來組成關鍵性的電路來達到高效能目標, 在非緊要的電路上使用低電壓元件庫來減少不必要的功率消耗。在這篇論文中, 會分別描述單一操作電壓與多操作電壓電路的成果。根據測試晶片的結果, 藉由操作電壓降低總功率消耗可以減少68個百分比。

With the advance of process technology, the purposes of the low power and high performance are focused in the nowadays circuit design. In digital circuit designs, the cell-based design follow is the most common way to implement the chip, and standard libraries play an important role in the cell-based flow. The standard logic cell library among different cell libraries is the major library to construct large of circuits. For digital circuit designers, using the low power cell library is the simplest and fast method to achieve the low power purpose. There are some low power techniques in the cell library, and the most efficient method is to reduce the supply voltage in the cell library.

In order to develop low voltage cell library, the standard cells need special design considerations in the low voltage condition. This thesis focuses on sequential cells of standard cells in low voltage condition. The main function of sequential cells is the data saving and clearing with the control of clock and reset signals, and then sequential cells have larger dynamic power consumption then the other cells. Consequently, it is necessary to research in sequential cells with low voltage condition. Additionally, the cell library characterization flow also needs the special setting for low voltage applications.
With low voltage affections, the cell library constraints become more serious.

For low power and high performance issues, the best application with low voltage cell library is the circuits with multiple power domains. Using the normal cell library in the critical circuits is for high performance consideration, and the non-critical circuits are implemented by the low voltage cell library in order to reduce unnecessary power consumption. In this thesis, it describes achievements of single-power and multi-power circuit designs. According to the results of the test chip, the total power consumption is decreased 68% by supply voltage dropping.

Introduction 1
1 Background.............................................1
2 Motivation of Thesis...................................2
3 Contents of Thesis.....................................3
A Review of Low Power Design Concept 5
1 Power Consumption Categories...........................5
2 Voltage Island.........................................8
3 Multi-Threshold Voltage CMOS Technology [7]............9
Sequential Cell Circuit Designs 11
1 Review of Some Sequential Circuit Structures..........11
1.1 Latch Circuit.......................................12
1.2 Flip-Flop Circuit...................................13
1.3 Scan Flip-Flop Circuit..............................19
2 Low Voltage Sequential Circuit Design Issues..........20
2.1 Low-Power Low-Voltage Special Design Consideration..20
2.2 Low Voltage Flip-Flop Design........................22
2.3 Essential Sequential Cell Design....................23
2.4 Flip-Flop Elementary Comparison.....................24
3 Sequential Cell Design for Low Voltage Library........25
3.1 Flip-Flop with Asynchronous Reset/Set...............25
3.2 Sequential Cell Optimization Methodology............27
3.3 Setup/Hold Timing Analysis..........................31
3.4 Flip-Flop Circuit Simulation and Comparison.........32
4 Special Cell Design...................................33
Low Voltage Standard Cell Library Development 39
1 Cell Library Characterization.........................39
1.1 Cell Library Generation Flow........................39
1.2 Characterization Reason and Flow....................40
1.3 Cell Library Simulation Environment Building........42
1.4 Library Characterization Parameters.................42
1.5 Modeling and Library Format.........................49
2 Low Voltage Cell Library Design.......................51
2.1 Analysis Procedure for Cell Design and Characterization Table...51
2.2 Low Voltage Library Setting and Attention...........52
2.3 Low Voltage Cell Circuit Modification...............54
3 Physical Cell Library.................................55
3.1 Physical Library Generation.........................55
3.2 Cell Library Specification..........................57
Test Chip Implementation and Measurement Results 59
1 Test Circuit for Power-Aware Application - AES Cipher Circuit...59
2 Multi-Power Test Circuit - A Channel Estimator for 802.16e...61
2.1 Introduction to Test Circuit........................61
2.2 Logic Design and Consideration......................63
3 Implementation of Multi-Power Test Circuit............64
3.1 Cell-Based Design Flow for Multiple Power Design....64
3.2 Voltage Island Synthesis............................66
3.3 Physical Design with Multiple Power Domain Floorplan...66
4 Simulation Results and Analysis.......................67
5 Dynamic Voltage Scaling Application...................69
Future Works and Conclusion 73
1 Future Works..........................................73
2 Conclusion............................................74

                                

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