碳化矽因為具備了優異的特性，例如寬能隙、大臨界電場、高電子飽和速度、高熱傳導係數，是用來製作高功率元件一個很有潛力的材料，但是熱氧化碳化矽當作絕緣層需要很高的溫度(大於1100oC)，基板和絕緣層接面特性因而嚴重地變差。
SiO2/SiC在這個研究主題，我們確認使用三氯氧磷退火技術將磷原子在碳化矽與氧化層介面鈍化的效果，並進一步我們嘗試沉積矽在碳化矽基板上並將上面的矽用低溫氧化(700℃ or 800℃)形成絕緣層，期望盡量避免氧化到基板。進一步研究三氯氧磷退火技術應用在此氧化層與氧化鋁堆疊至此氧化層。
沉積矽用低溫氧化並接著使用三氯氧磷退火(Si+LTO+POCl3)可將在距離導帶0.2 eV的介面能態密度下降至接近 1×1011 (eV-1cm-2 )。與高溫氧化基板接著使用三氯氧磷退火(HTO+POCl3)可達到的效果接近。使用(Si+LTO+POCl3)製程在MOSFET的場效遷移率可高於90 (cm2/V-s)。但是漏電流大而且良率低，(Si+LTO+POCl3+Al2O3) 絕緣層堆疊可以大幅改善漏電流問題且良率高很多。不過介面能態密度會有些許的上升至4×1011 (eV-1cm-2 )。場效遷移率可保留至60-70 (cm2/V-s)。
文獻上(HTO+POCl3)製程尚有可靠度的問題，我們初步使用一般操作電場強度3MV/cm stress在每個絕緣層製程。(Si+LTO+POCl3+Al2O3) 絕緣層堆疊有最少的臨界電壓飄移的問題。可能是磷參雜絕緣層較薄，另一個原因推測是氧化鋁材料特性帶有負電荷排斥電子吸附在絕緣層。

SiC has attracted significant attention for power semiconductor devices because of their superior physical and electrical properties: for instance, wide energy bandgap, large critical electric field, high electron saturation velocity, and high thermal conduc-tivity. However, thermal oxidation of SiC needs high temperature (>1100℃) and de-grades the interface property severely.
In this thesis, we confirm the effect of phosphorous passivation for the SiO2/4H–SiC interface employing POCl3 annealing. Furthermore, we try to deposit and oxidize Si with a low temperature (700℃ or 800℃) to grow gate dielectric. This way, minimal oxidation of SiC substrate can be anticipated. The POCl3 annealing technique is then applied to the SiO2. A gate dielectric stack structure with Al2O3 on top of the SiO2 is further studied.
In the process of depositing Si and low temperature dry oxidation followed by POCl3 annealing (Si+LTO+POCl3), the Dit is reduced to approximately 1×1011 (eV-1cm-2 ) at Ec-E=0.2eV similar to the process of high temperature dry oxidation followed by POCl3 annealing (HTO+POCl3). The μFE of MOSFET using Si + LTO + POCl3 process is higher than 90 (cm2/V-s), but the low yield rate and large leakage current are the major problems. The Si+LTO+POCl3 +Al2O3 gate dielectric stack im-proves the leakage current, and the yield is improved, although the Dit is slightly in-creased to 4×1011 (eV-1cm-2 ) at Ec-E=0.2eV, and the μFE can be retained approxi-mately 60-70 (cm2/V-s) .
The HTO + POCl3 technique has a reliability problem reported from the literature. In this study, a gate voltage corresponding to 3MV/cm is applied to stress and com-pare each gate dielectric process. The Si+LTO+POCl3 +Al2O3 gate dielectric process has the least Vth shift. It is attributed to the thinner thickness of phosphorus-doped SiO2 and the Al2O3 on top of it. One of the possible explanations is that the fixed neg-ative oxide charges in Al2O3 hinder electron injection.

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