切換電容導向之時鐘網路建構方法｜國立清華大學博碩士論文庫

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研究生：	王鼎雄 Ding-Hsiung Wang
論文名稱：	切換電容導向之時鐘網路建構方法 Switched Capacitance-Driven Clock Network Construction
指導教授：	王廷基 Ting-Chi Wang
口試委員:
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 資訊工程學系 Computer Science
論文出版年：	2006
畢業學年度：	95
語文別：	英文
論文頁數：	27
中文關鍵詞：	時鐘樹、時序差異、時鐘閘控、緩衝器尺吋設計、低耗能、超大型積體電路、實體設計
外文關鍵詞：	clock tree, clock skew, clock gating, buffer sizing, low power, VLSI, physical design
相關次數：	點閱：1 下載：0
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時鐘網路的功率消耗是晶片全部功率消耗的主要來源之ㄧ。為了提升產品的可使用性，低功率的技術變得非常重要，尤其是對於時鐘網路的低功率設計方法。時鐘閘控是降低數位電路動態功率消耗的有效方法。當暫存器內儲存的值不需要改變時，可以藉著關閉時脈訊號的切換來降低切換電容的值。除此之外，利用限制時序差異的時鐘樹可以縮短時脈訊號的線路長度，這也暗示了可以達到更低的功率消耗。在本篇論文，我們將整合時鐘閘控及限制時序差異時鐘樹的方法去建構出一個擁有最小功率消耗的閘控時鐘樹。首先，我們提出一個時鐘樹拓樸生成方法來產生擁有最小輸出負載的時鐘樹拓樸。其次，我們利用限制時序差異時鐘樹的繞線演算法嵌入產生的時鐘樹拓樸。最後，我們使用動態規劃的方式來調整緩衝器的尺寸，以期望更進一步最佳化功率的消耗。實驗結果顯示我們的方法能有效的降低動態功率的消耗。

Power dissipation in clock network distribution is one of the major sources of total power dissipation on a chip. In order to increase utility of the products, low-power techniques become very important, especially for clock network construction. Clock gating is an efficient way of reducing dynamic power consumption in digital circuits. It reduces switched capacitance by turning off transitions on a clock tree when the triggered registers do not need to change their values. Besides, bounded-skew clock tree is proposed to shorten the total wirelength of a clock net, implying lower power dissipation. Our work in this thesis is to construct a minimal power gated clock tree by integrating these two schemes. First, we propose a topology generation method to generate the clock tree topology with minimal output net loading. Second, we apply the bounded-skew clock routing algorithm to embed the generated topology. Finally, we perform buffer sizing by a dynamic programming approach to further optimize the power dissipation. The experimental results show that the algorithm is effective in reducing dynamic power consumption.

Content
誌謝辭..........................................ii
摘要............................................iii
Abstact..........................................v
Content..........................................vi
List of Figures .................................vii
List of Tables...................................viii
Chapter 1 Introduction ..........................1
Chapter 2 Problem Formulation....................6
Chapter 3 Methodology............................9
    3.1 Topology Generation .....................9
    3.2 Topology Embedding.......................14
    3.3 Buffer Sizing............................15
    3.4 The Flow of Our Methodology..............19
Chapter 4 Experimental Results...................20
Chapter 5 Conclusion.............................25
References.......................................26

List of Figures
Figure 1: Gated clock circuit  2
Figure 2: Unstable enable signal causes glitches  2
Figure 3: Gated clock circuit for glitch prevention  3
Figure 4: Convex Hull of S, CH(S)  10
Figure 5: Reference set and partition result  10
Figure 6: Relation graph  11
Figure 7: The dependent edges in the example of Fig. 6  12
Figure 8: The relation graph contains no dependent edge by removing from Fig. 7  13
Figure 9: The new relation graph generated after merging from Fig. 8  13
Figure 10: Levels in the clock tree  15
Figure 11: Update the output loading in the triangular shape  17
Figure 12: Algorithm for buffer sizing  18
Figure 13: The flow of our methodology  19


List of Tables
Table 1: The profile of each test case  20
Table 2: The comparison of the skew, total wire length, buffer numbers, and CPU time
between our methodology and BME before buffer sizing  22
Table 3: The power analysis before buffer sizing  22
Table 4: The comparison of the skew, total wire length, buffer numbers, and CPU time
between our methodology and BME after buffer sizing  23
Table 5: The power analysis after buffer sizing  24

                                

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[9] M. Edahiro, “Minimum Path-Length Equi-Distant Routing,” Proc. IEEE Asia-Pacific Conference on Circuits and Systems, pp. 41-46, 1992.
[10] J. Cong and C.-K. Koh, “Minimum-Cost Bounded-Skew Clock Routing,”Proc. IEEE Intl. Symp. on Circuits and Systems, Vol. 1, pp. 215-218, 1995.
[11] J. Cong, A. B. Kahng, C.-K. Koh and C.-W. A. Tsao, “Bounded-Skew Clock and Steiner Routing,”ACM Trans. on Design Automation of Electronics Systems, 3(3), pp. 341-388, 1998.
[12] J. G. Xi and W. W.-M. Dai, “Buffer Insertion and Sizing Under Process Variations for Low Power Clock Distribution,” Proc. ACM/IEEE Design Automation Conf., pp. 383-388, 1995.
[13] A. D. Mehta, Y.-P. Chen, N. Menezes, D.-F. Wong, and L. T. Pileggi, “Clustering and Load Balancing for Buffered Clock Tree Synthesis,” Proc. IEEE ICCD., pp. 217-223, 1997.
[14] R. Kay and L. T. Pillage, “EWA: Efficient Wiring-Sizing Algorithm. for Signal Nets and Clock Nets,” IEEE Trans. Computer-Aided Design, pp. 40-49, 1998.
[15] I.-M. Liu, T.-L. Chou, A. Aziz and D.-F. Wong, “Zero-skew clock tree construction by simultaneous routing, wire sizing and buffer insertion,” Proc. International Symposium on Physical Design, pp. 33-38, 2000.
[16] A. Farrahi, C. Chen, A. Srivastava, G. Tellez, and M. Sarrafzadeh, “Activity-Driven Clock Design,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, Vol. 20, No. 6, pp. 705-714, 2001.
[17] C. Chen, C. Kang, and M. Sarrafzadeh, “Activity-Sensitive Clock Tree Construction for Low Power,” Proc. ACM/IEEE International Symposium on Low-Power Electronics and Design, pp. 279-282, 2002.
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[19] M. Edahiro, “A Clustering-Based Optimization Algorithm in Zero-Skew Routing,” Proc. ACM/IEEE Design Automation Conf., pp. 612-616, 1993.

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