目前非揮發性記憶體在記憶體市場上相當普及，尤其以快閃記憶體為大宗。但快閃記憶體需要高電壓來進行寫入和消除資料，其操作速度偏慢，而且在製成微縮時會遭遇到耦合雜訊干擾和高偏移臨界電壓等問題。反觀下世代的非揮發性記憶體(例如:ReRAM、STT-MRAM…等)只需較低的操作電壓就能達到更好的效能，所以成為取代快閃記憶體的選擇。
伴隨著深度學習神經網路的快速發展以及行動裝置的廣泛應用，資料的計算及傳輸數量急遽成長。而傳統范紐曼(Von Neumann)架構受限於處理器和存儲器之間的帶寬限制，成為提升系統性能的最大瓶頸。所以記憶體內運算(CIM)的出現解決了這個問題，因減少資料的搬移量，使得處理效率大幅提升。同時搭配上非揮發性記憶體的儲存特性，非揮發性記憶體內運算架構(nvCIM)成為了具有高能源效率的運算方式。
本論文將探討非揮發性記憶體內運算所面臨的挑戰，並提出一個電流感測放大器去解決這些問題
1.在有限的高低阻值的比例下(R-ratio)，不同累加值(MACV)之間的感測裕度過小，會導致讀取良率降低。
2.為了提高準確率，非揮發性記憶體內運算架構必須支援多位元輸入和權重來確保運算後累加值(MACV)的位元數要夠多。隨著輸出的位元數越多，整體記憶體內運算的操作速度也會越慢，功率消耗提高。
因此在此篇論文中提出一個電流感測放大器，具有製程變異容忍及預先放大感測裕度的功能來提高讀取良率，且在一個操作時間內讀取兩位元(00/01/10/11)的資訊，相比傳統讀取一位元的架構，更能提高整體的操作速度，同時降低整體記憶體內運算的能量消耗。在大的累加電流下，能抑制等效偏移達傳統的2.1~2.6倍。在相同的感測裕度下，能提升至少16%的讀取良率，在多位元輸出像四位元和六位元輸出的架構下，和傳統感測電路相比，記憶體內運算巨集(macro)的速度快到1.36~1.43倍，同時使巨集能量消耗減少為1.2~1.28倍。
我們以容量為2Mb的電阻式記憶體來實作我們提出的架構。使用台積電55奈米製程。在正常操作電壓為1V下，量測提出之電路兩位元輸出的讀取速度為3.6奈秒而傳統一位元輸出的讀取速度為3.4奈秒，而應用在記憶體內運算架構具四位元輸入和四位元權重之乘積和的速度，在六位元輸出可達到22.2奈秒。

Non-volatile memory (NVM) is very popular on storage memory market nowadays. Especially, Flash memory has already been the mainstream of NVM. However, Flash memory requires high voltage to program and erase. The operation speed is still too slow, and meets the problems like coupling noise and large variation of threshold voltage for the scaling of Flash memory. On the other hand, emerging non-volatile memories have the ability to replace Flash memory due to their better performance for lower operating voltage.
Due to the rapid development of the deep neural network and the widely popular of variety mobile devices, the number of computing data and transmission has rapid grown up. However, the limited bandwidth between processor and memories has become the bottleneck to improve the system performance in conventional Von-Neumann computer architectures. Thus, the computing-in-memory (CIM) becomes a solution for improving the processing efficiency due to the data transfer reduction. With the benefits of non-volatile storage, the non-volatile based computing-in-memory (nvCIM) has the higher energy efficiency.
The paper will discuss the challenges for nvCIM, and proposed a current sense amplifier to solve these problems.
1.At a limited R-ratio, the sensing margin between neighboring MACV is too small and reduce the sensing yield.
2.To enhance the accuracy, nvCIM should support multibit input and weight to make sure the sufficient precision at output. With the output precision getting higher, it increases the access time and power consumption
Thus, this paper proposed a current sense amplifier with process variation tolerance and enhance the sensing margin. Due to the feature for sensing dual-bit at single operation cycle, the proposed scheme can enhance the sensing speed and reduce the energy consumption compared to conventional single-bit scheme. The equivalent offset suppression of proposed scheme is 2.1~2.6x smaller than conventional works under large summation current. The read yield can be improved at least 16%. By implementing in multibit input and weight nvCIM structure, the proposed scheme can achieve 1.36~1.43x faster speed and 1.2~1.28x lower energy consumption when output precision are 4bit and 6bit compared to conventional works.
Finally, the proposed scheme is verified in a 2Mb ReRAM macro fabricated in TSMC 55nm CMOS process. The operation voltage is 1V. The measured sensing time of proposed scheme is 3.6ns and conventional scheme is 3.4ns. The access time at 4bit input and 4bit weight nvCIM structure is 22.2ns with 6bit output.

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