應用於影像感測器具線性度校正功能之行平行十位元漸進式類比數位轉換器

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研究生：	蔡尚儒 Tsai, Shan-Ju
論文名稱：	應用於影像感測器具線性度校正功能之行平行十位元漸進式類比數位轉換器 A Column-Parallel 10-bit SAR ADC with Linearity Calibration for CMOS Image Sensor
指導教授：	謝志成 Hsieh, Chih-Cheng
口試委員:	邱進峰洪浩喬黃柏鈞謝志成
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2011
畢業學年度：	100
語文別：	英文
論文頁數：	115
中文關鍵詞：	行平行處理類比數位轉換器、漸進式類比數位轉換器、線性度校正
相關次數：	點閱：2 下載：0
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本論文提出一適用於CMOS影像感測器中行平行處理(Column-Parallel)之類比數位轉換器(Analog-to-Digital Converter, ADC)，並具有線性度校正功能。為降低單一類比數位轉換器之功耗，本論文採用漸近式類比數位轉換器(Successive Approximation ADC)的架構，並利用功耗較低的電容式數位類比轉換器(Capacitive Digital-to-Analog Converter)來產生類比數位轉換過程中所需的參考電位。
由於傳統電容式數位類比轉換器是造成漸進式類比數位轉換器面積過大的主要原因，在行平行處理的應用中由於要將之實現在行寬(Column Pitch)中，因此，本論文提出一多分段電容式數位類比轉換器(Multi-Segmented Capacitive DAC)以降低數位類比轉換器所占的面積，並提出一新的校正方式來修正因數位類比轉換器縮小所衍生出的線性度問題。本論文所提出自適應性重設組態(Adaptive Reset Configuration, ARC)的操作方式是將數位類比轉換器在重設時，使數位開關依產生的參考電位不同而調整至不同的開關組態，藉以消除數位類比轉換曲線上的非線性行為。
為驗證本電路，本論文利用0.18微米混合式訊號CMOS製程來實現一原型實驗晶片。經量測驗証後，差動非線性誤差由 +8.56 / -0.43 LSB 提升至 +1.67 / -1 LSB，積分非線性誤差由 +6.39 / -6.77 LSB 提升至 +3.31 / -4.36 LSB。本晶片在1.8V的電源供應下，消耗19.7微安培的電流，即35.46微瓦的功率。由於論文中晶片驗証結果不符預期，因此本論文中也探討了造成這些現象的原因，並提出解決的方式，以做為未來研究此類比數位轉換器時的基礎與參考。

This thesis presents a column-parallel analog-to-digital converter (ADC) with linearity calibration for CMOS image sensor. The architecture of the ADC is successive approximation ADC (SA ADC), which is a suitable architecture for low power consumption applications. A multi-segmented capacitive digital-to-analog converter is utilized to reduce both area and the power consumption of the DAC. A new calibration methodology is proposed to eliminate the linearity problem resulting from the segmented DAC.
Adaptive reset configuration (ARC) calibration methodology is proposed in this thesis. ARC eliminates the non-linear part of the transfer curve by setting different switch configuration during the reset cycle of the DAC according to different reference voltage acquired from the conversion.
A prototype experimental chip is fabricated by 0.18um mixed signal CMOS process. According to the measurement result, the differential non-linearity is reduced from +8.56 / -0.43 LSB to +1.67 / -1 LSB, and the integrated non-linearity is improved from +6.39 / -6.77 LSB to +3.31 / -4.36. The prototype ADC consumes 19.7uA, 35.46uW at 1.8V voltage supply. Some unexpected non-linearity was found, and the solutions are also discussed in this thesis.

摘要        I
Abstract        II
誌謝        III
Contents        IV
List of Figures    VI
List of Tables    X
Chapter 1 Introduction    1
1    Motivation    1
2    ADC Architecture for CMOS Image Sensors    2
3    Thesis Organization    4
Chapter 2 Column-Parallel ADC Overview    5
1    Single Slope ADC    5
1.1    Single Slope ADC [2]    5
1.2    Multi-Ramp Single-Slope ADC [3][4]    7
2    Cyclic ADC [5]-[7]    9
3    Successive Approximation ADC [8][9]    10
4    Delta-Sigma ADC [10][11]    11
5    Summary    13
Chapter 3 Successive Approximation Column-Parallel ADC    14
1    Sample-and-Hold Stage    15
1.1    Non-Ideal Effects of Sampling Switch [12]    16
1.2    Modified Sample-and-Hold Circuit    18
1.3    Design Consideration    21
2    Comparator    22
2.1    Topologies of Latched Comparator    23
2.2    Design Consideration    27
3    Successive Approximation Register    28
4    Digital-to-Analog Converter    30
4.1    Topologies of Capacitive DAC    30
4.2    Design Consideration    41
5    Simulation Results    47
6    Summary    50
Chapter 4 Linearity Calibration with Adaptive Reset Configuration DAC    51
1    Calibration with Adaptive Reset Configuration DAC    51
2    Operation Procedure Design    54
2.1    Pre-Conversion Operations    54
2.2    Data Conversion with Linearity Calibration    59
3    Characterization of the ARC Calibration and Related DAC Design Consideration    62
3.1    Characterization    62
3.2    Related DAC Design Consideration    64
4    Control System Design    67
4.1    Control of Locking Phase    68
4.2    Control of Quantizing Phase    69
4.3    Control of Data Conversion    70
5    Ramp Generator for Locking Phase    76
6    Simulation Results    77
7    Summary    80
Chapter 5 Chip Implementation and  Measurement Result    81
1    Chip Implementation    81
2    Simulation Results    83
3    Measurement Results    88
3.1    Measurement Environment    88
3.2    Measurement Results    89
3.3    Discussion    97
4    Summary    103
Chapter 6 Conclusion and Future Work    105
1    Conclusion    105
2    Future Work    106

                                

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