在現今超大型積體電路的設計，時鐘樹(Clock Tree)一直伴演著很重要的角色來同步化晶片中不同的元件，然而為了能夠達到同步化，構成時鐘樹的緩衝器(Clock Buffer)會在晶片中近乎同時充電或放電，造成了峰電流(Peak Current)以及局部電源/接地端的雜訊(Local Power/Ground Noise)，嚴重地影響了電路的效能(Performance)及可靠性(Reliability)。

因此，過去的研究提出了信號極性分配(Signal Polarity Assignment)的方法，有效地控制時鐘樹上的緩衝器的極性，避免所有的緩衝器同時充電或放電來解決這個問題。但是，由於沒有考慮到時間的資訊(Timing Information)，先前的方法反而嚴重地增加了時序差異(Clock Skew)，使電路的效能大幅下降，必須再進一步地修正時序差異；有鑑於此，我們知道考慮時間的資訊是有其必要性的。

在這篇論文中，首先我們會展現觀察到的現象，發現不需要考量到整個時鐘樹全部的緩衝器，僅針對特定的緩衝器分配極性即可解決峰電流以及局部電源/接地端雜訊的問題；而後，我們提出了新穎的信號極性分配方法，不僅能大量地減少峰電流及局部電源/接地端的雜訊，同時也有效地控制時序差異。

實驗結果顯示，相較於原來時鐘樹的時序差異，在平均上，我們的方法可以得到92%的時序差異，在另一方面，先前被提出的三個信號極性分配方法-分割(Partition)、最小生成樹(MST)、相配(Matching)，則分別得到231%、265%、及276%的時序差異，並且我們的方法在峰電流及電源/接地端雜訊的處理上亦能與先前方法一樣地有效。

In modern sequential VLSI designs, clock tree plays an important role in synchronizing different components in a chip. To reduce peak current and power/ground noises caused by clock network, assigning different signal polarities to clock buffers is proposed in previous work. Although peak current and power/ground noises are minimized by signal polarities assignment, an assignment without timing information may increase the clock skew significantly. As a result, a timing-aware signal polarities assigning technique
is necessary. In this thesis, we propose a novel signal polarities assigning technique which can not only reduce peak current and power/ground noises simultaneously but also render the clock skew in control. The experimental
result shows that the clock skew produced by our algorithm is 92% of original clock skew in average while the clock skews produced by three algorithms (Partition, MST, Matching) [8] are 231%, 265%, and 276%, respectively. Moreover, our algorithm is as efficient as the three algorithms of [8] in reducing peak current and power/ground noises.

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