在石油燃料及天然氣的價格逐漸升高，對替代能源的需求也日益增加。太陽能被視為下一代之主流能源，其應用亦被廣泛討論。然而，如何更有效率地提升太陽能轉換效率也成為重要議題。為了提升在太陽能光電系統在受到遮蔽時的輸出功率，我們使用分散式太陽能光電系統之架構，並且搭配最大功率追蹤功能，使每一塊太陽能板都能操作在其最大功率輸出點。內部的數位訊號處理器包含了最大功率追蹤以及電流預測之功能。此外，本實驗亦提供介面電路作為類比環境及數位環境之溝通橋樑。本論文將會著重在討論介面電路包含類比數位轉換器以及數位脈波寬度調節器之設計。
在介面電路當中包含了8 位元之逐步漸進式類比數位轉換器，並且針對降低內部切換功率及降低所使用電容面積大小做了精確的設計。在逐步漸進操作上使用了非同步操作方式以達到降低其所需要的操作速度及控制電路之功率消耗。
另一方面，混和式數位脈波寬度調變器提供二個頻道同時控制直流升壓轉換器之上橋及下橋之開關。在同步開關的切換式轉換電路的實現上，加入空白時間以避免上下橋開關同時導通產生瞬間電路短路造成漏電流，使得轉換效率降低。此混和式數位脈波寬度調變器亦包含了矯正電路抵抗製程偏移所造成的影響，並且配有自動重啟功能，降低整體功率消耗。
本實驗使用TSMC 0.25-μm HV CMOS 1P3M 製程當中的2.5V 元件實現，晶片大小為1.7mm × 1.9mm，並且成功的操作在分散式太陽能光電系統平台上。

As oil and gas prices have risen, the demand for alternative energy sources also increased. Photovoltaic (PV), the third important renewable energy has been widely discussed; however, how to transfer solar energy efficiently has become the top issue. In order to deal with the performance degradation caused by sunlight blocking, we used a distributed panel photovoltaic power conversion system, which utilizes maximum power point tracking (MPPT) algorithm to achieve the optimal power conversion rate when being deployed individually on each panel. An internal digital signal processor (DSP) is used to implement MPPT algorithm and predict current to regulate DC/DC boost converter. Moreover, an interface for connecting analog environment and digital control logic is also required. This thesis will mainly focus on designing this interface circuit, which includes an analog to digital converter (A/D Converter) and a digital pulse width modulation (digital PWM).
A successive approximation analog to digital converter (SA-ADC) with 8-bit resolution is used in this circuit. The circuit structure is specifically designed for saving the switching energy and plate area of capacitor. The successive approximation algorithm is controlled asynchronously for reducing the power being consumed by clock generator and control circuits.
This digital pulse width modulator (digital PWM) provides two control channels for switching high-side and low-side switches of DC/DC boost converter. The leakage of this boost converter is effectively suppressed by tuning the dead time between switches. This digital PWM is accompanied with calibration circuit to overcome the process variation and self-rest circuit to lower the power consumption.
This interface circuit was fabricated by TSMC 0.25μm HV CMOS 1P3M process, and 2.5V devices among this process are used. This chip area is 1.7mm×1.9mm, and has been verified in a real PV power conversion prototype.

[1] C. Deline, “Partially shaded operation of multi-string photovoltaic systems,” in Proc. IEEE Photovoltaic Spec. Conf., 2010, pp. 000 394–000 399.
[2] W. Damm, D. Heinemann, and D. Pukrop, “Power losses in PV arrays due to variations in the IV characteristics of PV modules,” 1995. [Online]. Available: www.energiemeteorologie.de/publications/solar/conference/1995/Power Losses in PV Arrays Due To Variations in the I V Characteristics of PV Modules.pdf
[3] S. Wenham, Applied photovoltaics. Earthscan/James & James, 2007.
[4] G. Walker and P. Sernia, “Cascaded DC-DC converter connection of photovoltaic modules,” IEEE Trans. Power Electron., vol. 19, no. 4, pp. 1130–1139, Apr. 2004.
[5] L. Linares, R. Erickson, S. MacAlpine, and M. Brandemuehl, “Improved energy capture in series string photovoltaics via smart distributed power electronics,” in Proc. IEEE Appl. Power Electron. Conf. Expo., 2009, pp. 904–910.
[6] F. Gonz´alez-Longatt, “Model of photovoltaic module in matlab,” 2do Congreso iberoamericano de estudiantes de ingenieracute ; a el ectrica, electr oica y computaci o, II CIBELEC, vol. 2005, pp. 1–5, 2005.
[7] T. Esram and P. Chapman, “Comparison of photovoltaic array maximum power point tracking techniques,” IEEE Trans. Energy Convers., vol. 22, no. 2, pp. 439–449, Feb. 2007.
[8] J. Chen, A. Prodic, R. Erickson, and D. Maksimovic, “Predictive digital current programmed control,” IEEE Trans. Power Electron., vol. 18, no. 1, pp. 411–419, Jan. 2003.
[9] J. McCreary and P. Gray, “All-MOS charge redistribution analog-to-digital conversion techniques Part I,” IEEE J. Solid-State Circuits, vol. 10, no. 6, pp. 371–379, 1975.
[10] B. Ginsburg and A. Chandrakasan, “An energy-efficient charge recycling approach for a SAR converter with capacitive DAC,” in Proc. IEEE Int. Symp. Circuits and
Systems (ISCAS), 2005, pp. 184–187.
[11] M. Yoshioka, K. Ishikawa, T. Takayama, and S. Tsukamoto, “A 10b 50MS/s 820 W SAR ADC with on-chip digital calibration,” in Proc. IEEE Int. Solid-State Circuits
Conf. (ISSCC) Dig. Tech. Papers, 2010, pp. 384–385.
[12] E. Alpman, H. Lakdawala, L. Carley, and K. Soumyanath, “A 1.1 V 50mW 2.5 GS/s 7b time-interleaved C-2C SAR ADC in 45nm LP digital CMOS,” in Proc. IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, 2009, pp. 76–77.
[13] C. Liu, S. Chang, G. Huang, and Y. Lin, “A 10-bit 50-MS/s SAR ADC with a monotonic capacitor switching procedure,” IEEE J. Solid-State Circuits, vol. 45, no. 4, pp. 731–740, Apr.
[14] Y. Zhu, C.-H. Chan, U.-F. Chio, S.-W. Sin, U. Seng-Pan, R. P. Martins, and F. Maloberti, “A 10-bit 100-MS/s reference-free SAR ADC in 90 nm CMOS,” IEEE J. Solid-State Circuits, vol. 45, no. 6, pp. 1111–1121, Jun.
[15] M. Yip and A. Chandrakasan, “A resolution-Reconfigurable 5-to-10b 0.4-to-1V powerscalable SAR ADC,” in Proc. IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. tech.
Papers, 2011, pp. 190–192.
[16] J. Tsai, Y. Chen, M. Shen, and P. Huang, “A 1-V, 8b, 40MS/s, 113 W chargerecycling SAR ADC with a 14 W asynchronous controller,” in IEEE Trans. VLSI Syst., 2011, pp. 264–265.
[17] A. Abo and P. Gray, “A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital
converter,” IEEE J. Solid-State Circuits, vol. 34, no. 5, pp. 599–606, May 1999.
[18] P. Harpe, C. Zhou, X. Wang, G. Dolmans, and H. de Groot, “A 30fJ/conversion-step
8b 0-to-10MS/s asynchronous SAR ADC in 90nm CMOS,” in Proc. IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, 2010, pp. 388–389.
[19] M. Van Elzakker, E. Van Tuijl, P. Geraedts, D. Schinkel, E. Klumperink, and B. Nauta,“A 1.9 W 4.4 fJ/conversion-step 10b 1MS/s charge-redistribution ADC,” in Proc.IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers. IEEE, 2008, pp.244–610.
[20] A. Syed, E. Ahmed, D. MaksimoviC, and E. Alarcon, “Digital pulse width modulator architectures,” in IEEE Power Electron. Spec.Conf., vol. 6, 2004, pp. 4689–4695.
[21] B. Patella, A. Prodic, A. Zirger, and D. Maksimovic, “High-frequency digital PWM controller IC for DC-DC converters,” IEEE Trans. Power Electron., vol. 18, no. 1, pp.438–446, Jan. 2003.
[22] H. Chang, J. Lin, C. Yang, and S. Liu, “A wide-range delay-locked loop with a fixed latency of one clock cycle,” IEEE J. Solid-State Circuits, vol. 37, no. 8, pp. 1021–
1027, Aug. 2002.
[23] J. Maneatis, “Low-jitter process-independent DLL and PLL based on self-biased techniques,” IEEE J. Solid-State Circuits, vol. 31, no. 11, pp. 1723–1732, Nov. 1996.
[24] A. Chandrakasan, W. Bowhill, and F. Fox, Design of high-performance microprocessor circuits. Wiley-IEEE Press, 2000.