在處理器設計的研究，動態電壓頻率調節機制常被用於達到效能與耗能的良好平衡，現在也有許多的處理器會搭載不同的動態電壓頻率調節機制。這些方法會適時地讓處理器和快取降到比較低的電壓與頻率來降低系統的功率。但在我們調降電壓的同時，快取本身的可靠性也會大幅地下滑。因此，系統能調降的電壓範圍會受到可靠性的限制。為此，我們提出了一個以快取使用率為核心的動態電壓頻率調節機制，搭配7T/14T SRAM [1] 的快取來改善可靠性。在我們的方法中，即使在更低的電壓，系統依舊能可靠的運作。比起傳統的動態電壓頻率調節機制，為了和7T/14T SRAM架構理想的結合，我們考慮了不只是平均每個指令的週期數，更考慮了一個新的數據 – 快取使用率，這數據我們會用來衡量快取當前容量的效率。對於我們提出來的方法我們設計了一連串的實驗，主要有以下三個向度：系統可靠性、消耗能量、系統效能。實驗結果指出跟前人的線上學習的動態電壓頻率調節方法 [2] ，我們的方法比起前人在系統可靠性從原本的平均每天0.246個快取記憶體錯誤降低到0.113，並且在能量消耗少了2.2%，在效能提升了5.5%；跟前人搭載更為不可靠的低電壓的結果比較，在可靠性上更是從原本的平均每天522.85個快取記憶體錯誤降低到0.113，而且在能量消耗上面減少了1.5%，效能也提升了5.5%。

Dynamic Voltage-Frequency Scaling (DVFS) has been proposed for a good balance between power and performance in processor design. Various DVFS methods are now applied
to modern processor designs. These techniques sometimes make processors and cache operate at lower supplying voltage for energy saving. But the scaled-down supplying voltage greatly decreases the reliability of cache at the same time. To address this issue, we propose a cache-utilization based DVFS mechanism utilizing 7T/14T cache architecture [1] for reliability enhancements. In our method, under ultra-low voltage, the cache system can still operate in a reliable state. Different from conventional DVFS, in order to combine perfectly
with 7T/14T cache architecture, we consider not only CPI behaviors but also a new metric -- cache utilization, which we use to estimate the effectiveness of cache capacity. A set of experiments to examine our method are conducted in three degrees: reliability, power, and performance. The results show that compared to the online learning DVFS method [2] using safe supply voltage, reliability by our method improves in average from 0.246 ECC errors per day to 0.113, with 2.2% energy reduction and 5.5% speed-up in performance. Moreover, compared to the online learning DVFS method using ultra-low voltage, reliability by our method improves in average from 522.85 ECC errors per day to 0.113, and 1.5% reduction in energy
and 5.5% speed-up in performance.

1] Hidehiro Fujiwara, Shunsuke Okumura, Yusuke Iguchi, Hiroki Noguchi, Hiroshi
Kawaguchi, , and Masahiko Yoshimoto. A 7t/14t dependable sram and its array struc-
ture to avoid half selection. In Proceedings of International Conference of VLSI Design,
pages 295-300, 2009.
[2] Gaurav Dhiman and Tajana Simunic Rosing. Dynamic voltage frequecy scaling for
multi-tasking systems using online learning. In Proceedings of the International Sympo-
sium on Low Power Electronics and Desing, 2007.
[3] Brian Je. Big.little system architecture from arm: saving power through heterogeneous
multiprocessing and task context migration. In Patrick Groeneveld, Donatella Sciuto,
and Soha Hassoun, editors, DAC, pages 1143-1146, 2012.
[4] James Charles, Preet Jassi, Ananth Narayan S, Abbas Sadat, and Alexandra Fedorova.
Evaluation of the intel core i7 turbo boost feature. In IEEE International Symposium
on Workload Characterization, pages 188-197, 2009.