在現代行動通訊系統中採用了所謂正交分頻多工擷取(OFDMA)的技術。在一個OFDMA的系統中，次載波被分成多個資源區塊(resource block)且分配給多個使用者使用，根據第三代合作夥伴計劃-長期演進技術(3GPP-LTE)的規格當中，一個resource block單位內有12個次載波，對於使用者只會使用到一個OFDM symbol中的部份次載波，所以我們不需要把完整的OFDM符元(symbol)計算出來，假如能根據使用者所分配到的resource block，把對應的載波計算出來，則將能有效率地減少功率的消耗與運算的時間。在本研究當中，我們提出一套能根據不同resource block的使用方式。此外我們發現在3GPP TS36.213的規格中所定義的resource block的分配方式也是相同的原理。所以我們設計一個以記憶體為基礎的快速傅立葉轉換處理器(cached-memory-based FFT)，只運算分配給使用者需要的部份。根據處理器的特性，設計出對應的演算法，會根據不同的分配方式來調整。依據3GPP-LTE的規格，我們設計了一個可以支援128點到2048點的快速傅立葉轉換處理器，其中特別的地方是FFT為1536點的運算，不同於一般的FFT點數為2的冪次方，在1536點內需要做radix-3 butterfly的處理，因此我們採用了一個處理運算元(processing element)以butterfly為radix-22的架構下，加入控制使得可以支援radix-3 butterfly的運算。而twiddle factor乘法器佔據了全部butterfly運算中很大的運算比例，所以為了降低功率的消耗，我們採用了一個能根據FFT運算中信號的動態範圍和使用之不同constellation跟FFT點數做調整之功率可感知的乘法器。此外，我們採用Block-floating point 的架構來增進cached-FFT處理器的SQNR(signal-to-quantization-noise-ratio)，使得整體的性能提升。最後，我們使用TSMC 18的技術實現硬體實作。根據設計的cached-FFT處理器，最多可以降低功率消耗到原先完整FFT運算的64.38％。

In communication systems with the orthogonal frequency division access (OFDMA) technology, multiple users can share the same bandwidth offered by only one base station, which means the resource allocation technique is highly emphasized. Since each user allocates partial bandwidth, power consumption can be reduced by performing partial fast Fourier transform (FFT). In this work, we proposed the algorithm of resource block allocation technique. According to the proposed algorithm, we designed a low-cost and low-power FFT structure based on cached memory; besides, a scalable and power-aware processing element was adopted for twiddle factor multiplication. The proposed butterfly processor can support the radix-3 operation in order to perform 1536-point FFT in the mode 5 of the 3GPP long term
evolution (3GPP-LTE) standard. Moreover, the block-floating point (BFP) algorithm was applied to acquire better signal-to-quantization-noise ratio (SQNR). Since the energy dissipation is correlated with operational cycles, we proposed a reconfigurable architecture of the FFT processor which is capable of reducing operational cycles by switching controlling circuits depending on different conditions. Finally, the cached-FFT processor was implemented with TSMC 0.18um 1P6M CMOS technology, and the measurement of energy dissipation ranged from 1.23 to
4.24nJ per FFT point.

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