近幾年來，系統晶片設計的發展非常地快速，也越來越複雜，晶圓廠的製造技術也必須配合電路設計的發展，製造技術不斷的演進過程中，許許多多的問題也隨之產生。晶片上的金屬連線將會是以後設計電路的主要瓶頸，晶片上金屬連線所帶來不必要的寄生電阻、寄生電容、寄生電感，將會對整體電路的效能影響非常大。對於以前電路設計者來說，他們只有探討寄生電阻和寄生電容所帶來的效應，可是未來的晶片速度將會持續上升達到數個GHz，此時的寄生電感將會變的很重要，如果不考慮寄生電感時，則在做模擬分析的時候將會失去準確性，進而造成整個晶片壞掉。在這一篇論文中，我們將使用FastHenry當作計算電感的標準，使用不同的傳輸線結構，進而提出ㄧ個方法去建立電感表格。實驗結果發現到電感是呈現單調的變化，因此可以使用內插法或是外插法求出其他不在電感表格內的電感，本論文的電感表格雖然涵蓋多種傳輸線的結構，但是真實的電路中更複雜的傳輸線則可以使用簡易的演算法來逼近，而且誤差值均為負的，本論文也在這方面的應用提出方法並且解釋負的誤差原因。晶片電感表格的建立將會有利於電路設計者去設計重要的電路傳輸線，未來則可以提供更多的傳輸線結構模型的自感與互感給電路設計者使用，並且採用本文尚未探討的90奈米矽晶圓量測資料來証明使用FastHenry來算奈米電感是準確的，例如S參數的量測。

In recent years, SoC design improves quickly and becomes more and more complex. Since manufacturing technique of fabrication must follow the improvement of circuit design, many problems are generated during this improving progress. One of them is on-chip interconnect induced issue, which is related to parasitic resistance, parasitic capacitance, and parasitic inductance. And it is regarded as future main bottleneck of circuit design due to its bad influence on the performance of global circuit.
In the past, circuit designers just considered the effects of parasitic resistance and parasitic capacitance. But the speed of chip will achieve several GHz, parasitic inductance will become very important. If we don’t consider the parasitic inductance, we will loose the accuracy while doing simulation and the chip will fail. In this thesis, we will use FastHenry as our standard of inductance simulation, use different structures of transmission line, and propose our method to build inductance table then. We discovered the inductance is monotonic in experiment results. So, we conclude that applying interpolation to calculate the inductance which is not in this inductance table will work in the case. Though there are more complex transmission lines in real circuit, one can use simple algorithm to get simulated inductance with negative errors based on the inductance table here which covers many kinds of transmission line structure. In addition, we also proposed a method on this application and explain why the errors are negative. In conclusion, on-chip inductance table will be useful for circuit designer to design critical transmission line. In the future, we can propose more transmission line structures with self and mutual inductances for circuit designer and use 90nm silicon wafer measurement such as S-parameter to prove FastHenry is accurate in nanometer inductance extraction.

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