簡易檢索 / 詳目顯示

研究生: 蔡函育
Tsai, Han-Yu
論文名稱: Modeling and Validating Time-Domain and Frequency-Domain Transmission Line Parameters
模擬與驗證時域頻域傳輸線模型參數
指導教授: 曾孝明
Tseng, Shiao-Min
張克正
Chang, Keh-Jeng
口試委員: 唐經洲
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電子工程研究所
Institute of Electronics Engineering
論文出版年: 2011
畢業學年度: 100
語文別: 中文
論文頁數: 70
中文關鍵詞: 傳輸線RLCKG模型散射參數相互轉換法共同設計方法頻域參數時域參數差動傳輸共模傳輸三維電磁模擬軟體
外文關鍵詞: Transmission Line, RLCKG model, S-parameter, Two-way Conversion, Co-design, Differential Signal, Common Signal, IE3D, FastHenry, Clever
相關次數: 點閱:1下載:0
分享至:
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報
  • 隨著電路訊號的上升時間越來越短,系統的操作頻率已達到十億赫茲(GHz)的範圍,所以必須把金屬連接當作傳輸線來看。在封裝、印刷電路板和超大型積體電路的低頻設計中,連接著不同元件之間的金屬連接線還不會影響訊號傳遞的表現;但在射頻設計中,已必須使用準確且有效率的方法進行模擬。因為在產品中使用射頻已經是一個趨勢,所以在產品封裝時所使用的連接線必須視為傳輸線來看。製程越來越先進,電路也越來越複雜,預先共同設計的方法因此被提出,而利用準確的傳輸線模型,不但可使產品降低成本同時提升電路表現。
    乘載訊號頻率在高頻電路系統中增加,偶合效應以及電磁干擾等問題逐漸出現。為了改善訊號的完整性,因而開始使用兩條平行傳輸線構成的差動傳輸模式訊號。在先進積體電路封裝技術中,不僅兩個端點的網路分析已經行之有年,就連四個端點的用量也越來愈頻繁。
    在射頻訊號或是微波電路分析中,頻域的散射參數已經被廣泛的使用,可描述多個端點的網路分析;射頻參數可以簡單的利用矩陣的方式表達。而現今工業界也都已經有建立量測射頻參數的儀器。對電路設計者而言,利用類似SPICE這種軟體工具驗證時域的訊號也是相當必須的。電子設計自動化軟體必須利用準確地的傳輸線等效電路模型才可以執行正確的電路模擬,否則將會失去模擬的意義。在這篇論文當中,傳輸線的電性特徵是利用散佈式RLCGK當作模型,且這些電性參數是利用三維的電磁模擬軟體抽取。
    我們在此論文中提出了可以在頻域和時域間相互轉換的方法,利用HSPICE和Matlab量化這些數值且進行驗證的工作。如此,電路設計者更容易觀察高頻的傳輸線的行為,並且減少誤用參數的可能性,進一步提升設計電路的便利性與準確性。


    ABSTRACT (英文摘要) I 目錄 III 圖目錄 V 表目錄 VIII 第一章 簡介 1 1.1 前言 1 1.2 系統單晶片( SYSTEM ON CHIP)與系統級封裝(SYSTEM IN PACKAGE) 3 1.3傳輸線(TRANSMISSION LINE) 4 1.4 射頻散射S參數 5 1.5動機與驗證流程 6 第二章 背景介紹和相關研究 7 2.1傳輸線應用 7 2.2 傳輸線理論 8 2.3 時域電性參數 10 2.3.1電感矩陣 10 2.3.2電容矩陣 15 2.3.3電阻、電導 16 2.4 傳輸線分散式模型 17 2.5耦合與串音 18 2.5.1 奇波傳輸(ODD MODE) 19 2.5.2 .偶波傳輸(EVEN MODE) 20 2.6 訊號完整性 22 2.7阻抗匹配 22 2.8製程變異 23 2.9電磁軟體 25 2.9.1 FASTHENRY 25 2.9.2 CLEVER 26 2.9.3 IE3D 26 2.10 HSPICE 27 2.11 MATLAB 27 第三章時域頻域轉換驗證方法 28 3.1頻域與時域轉換流程 28 3.2 頻域轉換時域方法 29 3.2.1 兩端點2-PORT轉換(S2-FUN.) 29 3.2.2 四端點4-PORT轉換(S4-FUN.) 30 3.3 時域轉換頻域方法 32 3.3.1 兩端點2-PORT轉換 32 3.3.2 四端點4-PORT轉換 33 第四章 頻域時域相互轉換驗證結果 36 4.1 兩端點2-PORT傳輸線頻域時域驗證 36 4.2 四端點4-PORT傳輸線頻域時域驗證 42 第五章 結論 50 5.1 CO-DESIGN合成結果 50 5.2 製程變動對損耗的影響 51 5.3 阻抗匹配 54 5.4 頻域時域相互轉換問題與解決 54 5.4.1分散式布局圖 54 5.4.2 .頻域參數的低頻行為 55 5.4.3 頻域參數曲線趨勢 56 5.4.4 小尺寸幾何圖形 56 第六章 未來工作 57 6.1 自動圖形化介面 57 6.2 多端點頻域轉時域 57 6.3 更完整垂直堆疊系統級封裝 57 參考文獻 59 附錄 62 附錄 1 傳輸線的分類 62 附錄2 FASTHENRY INPUT FILE FOR 2-PORT LEVEL 0金屬線 63 附錄3 FASTHENRY INPUT FILE FOR 4-PORT LEVEL 1金屬線 65 附錄4 CLEVER INPUT FILE 68 附錄5 MATLAB 4-PORT頻域轉時域方法 69

    [1] Intel Corporation, "Risk Factors," Available at http://download.intel.com/newsroom/kits/22nm/pdfs/22nm-Announcement_Presentation.pdf
    [2] IBM Research, "Copper Interconnects The Evolution of Microprocessors," Available at http://www.ibm.com/ibm100/us/en/icons/copperchip/
    [3] John P. Uyemura, Introduction to VLSI Circuits and Systems. John Wiley & Sons, New York, 656 pages, 2002.
    [4] Richard K. Ulrich and William D. Brown, Advanced Electronic Packaging, 2nd John Wiley & Sons Inc, pp. 3-8, 2005.
    [5] C.R. Paul, Inductance: Loop and Partial, John Wiley, Hoboken, N.J., 2010.
    [6] C. R. Paul, Analysis of Multi conductor Transmission Lines, New York: Wiley, 1994.
    [7] Gerard V. Kopcsay, Byron Krauter and David Widiger et al., "Comprehensive 2-D inductance modeling approach for VLSI interconnects: frequency-dependent extraction and compact circuit model synthesis," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 10, No. 6, December 2002.
    [8] Pozar D.M. Microwave Engineering Third Edition, John Wiley & Sons Inc, 2005.
    [9] Yen, Ching-Yang, "Proposing A New Fast 3D Electromagnetic-based RLC Extraction Software Platform for 3D-IC and System-in-Package Designs," M.S. Dissertation, Department of Computer Science, National Tsing Hua University, Taiwan, 2009.
    [10] E. Bogatin, Signal Integrity Simplified, Prentice Hall, Upper Saddle River, New Jersey, September, 2003.
    [11] Eric Bogatin, " Differential Impedance finally made simple," Available at http://www.ewh.ieee.org/r5/denver/rockymountainemc/archive/2000/diffimp.pdf
    [12] M. Kamon et al., FastHenry USER’s GUIDE, version 3.0, Massachusetts Institute of Technology, Cambridge, Massachusetts, November 1996.
    [13] Silvaco Inc. Clever Reference Manual, Silvaco Inc., Santa Clara, California, Nov. 2003.
    [14] Kilomega online, "Zeland IE3D," Available at http://www.kilomega.com/wiki/index.php? doc-view-205. html
    [15] Chen, Hsin-Hsieh, "Rigorous design, modeling and analysis of high-frequency VLSI clock trees," M.S. Dissertation, Department of Electrical Engineering, National Tsing Hua University, Taiwan, 2011.
    [16] Wikipedia, "MATLAB," available at http://zh.wikipedia.org/wiki/MATLAB
    [17] Yungseon Eo and William R. Eisenstadt, "High-speed VLSI interconnect modeling based on S-parameter measurements," IEEE Trans. Comp., Hybrids, Manufact. Technol., Vol. 16, No. 5, August 1993.
    [18] W. R. Eisenstadt and Y. Eo, “S-parameter-based IC interconnect transmission line characterization,” IEEE Trans. Comp., Hybrids, Manufact. Technol., vol. 15, no. 4, pp. 483–490, Aug. 1992.
    [19] Dongchul Kim and Yungseon Eo, “S-parameter-measurement-based time-domain signal transient and crosstalk noise characterizations of coupled transmission lines,” IEEE Trans. Adv. Packag., VOL. 32, NO. 1, February 2009.
    [20] Kai Kang et al.,“On-chip coupled transmission line modeling for millimeter-wave applications using four-port measurements,” IEEE Transactions on Advanced Packaging, vol. 33, no. 1, february 2010.
    [21] R. Mongia, I. J. Bahl, and P. Bhartia, RF and Microwave Coupled-Line Circuits, Artech House, London, U.K, pp. 123–139, 1999.
    [22] Jun-Fu Huang et al., “Modeling and validating gigahertz-level time-domain multi-port sub-65nm transmission-line parameters,” Proceedings of the 25 The VLSI Multilevel Interconnection Conference (VMIC), Fremont, USA, October 2008.
    [23] H. B. Bakoglu, Circuits, Interconnections, and packaging for VLSI. Reading, MA: Addison-Wesley, pp. 291-298, 1990.
    [24] Keh-Jeng Chang, “Accurate on-chip variation modeling to achieve design for manufacturability,” in Proceedings of the 4th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC), pp. 219- 222, 19-21 July 2004.
    [25] J. Yao et al.,“Giga-hertz-level electromagnetic field analysis for equivalent inductance modeling of high-performance SoC and SiP designs,” Journal of Semiconductor Technology and Science, Vol. 5, No. 4, December 2005.
    [26] Xiaoning Qi, Bendik Kleveland, Zhiping Yu, Simon Wong, Robert Dutton and Tak Young, “On-chip inductance modeling of VLSI interconnects,” in Digest of Technical Papers IEEE International Solid-State Circuits Conference (ISSCC), pp. 172–173,2000.

    無法下載圖示 全文公開日期 本全文未授權公開 (校內網路)
    全文公開日期 本全文未授權公開 (校外網路)

    QR CODE