近幾年來，我們越來越關注在嵌入式系統上使用動態指令翻譯的技術。然而，在嵌入式系統上面使用這項技術時會遭遇到一些困難，因為在嵌入式系統上的記憶體資源往往是有限的，所以二進制指令被重新翻譯的次數也會相對增加，這種情況會造成系統效能嚴重下降。為了改善系統效能，異構記憶體指令快取架構被提出來去解決這個問題，他結合了主記憶體和快取記憶體去組成系統所需要的指令快取架構，雖然異構記憶體指令架構可以很好的被運作在一些應用程式上面，但是它忽略了程式執行的特性，將一些有可能會被大量執行的二進制指令放在主記憶體上，而不是放在快取記憶體上面，使得程式效能受到限制。為了解決這個問題，我們提出了增強異構記憶體指令快取的管理方法，這個方法可以有效的考慮程式執行的行為，進而去最佳化翻譯過的代碼在指令快取架構中的配置，實驗結果顯示，該管理方法可以有效地使快取命中率從 49.48%增加到95.06%，這也讓整體的系統效能有了42.68%的提升。

Recently, DBT has gained much attentions on embedded systems. However, the memory resource in embedded systems is often limited. This leads to the overhead of code re-translation and causes significant performance degradation. To reduce this overhead, Heterogeneous Code Cache (HCC), is proposed to split the code cache among SPM and main memory to avoid re-translation of code fragments. Although HCC is effective in handling applications with large working set, it ignores the execution frequencies of program fragments. Frequently executed program fragments can be stored in main memory and thus causes performance loss. To address this problem, an enhanced Heterogeneous Code Cache management scheme which considers program behaviors is proposed in this thesis. Experimental results show that the proposed management scheme can effectively improve the access ratio of SPM from 49.48% to 95.06%. This leads to 42.68% improvement of performance as compared with the management scheme proposed in the previous work.

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