本研究為將迴圈概念應用在游標尺延遲線之時間數位轉換器，以改善游標尺延遲線架構在面積、功率消耗、及元件匹配度等方面所遭遇的問題，同時減少延遲元件的數目。在第一階段將一條游標尺延遲線當作是一個單位的量測標準進行多次量測，並用計數器記錄量測圈數，然後將殘餘時間進入第二階段使用游標尺進行量測，最後由解碼器將溫度計碼型式的輸出轉為二進位型式的輸出，得到最後的結果。游標尺延遲線所使用的延遲元件由延線鎖相迴路來控制其偏壓，使得延遲元件能夠穩定提供電路所需的兩種延遲時間。
時間數位轉換器使用TSMC CMOS 0.18um 1P6M製程來實現，由延遲元件之延遲時間、信號轉換時間及誤差分析的考量，選擇參考時脈的頻率為360MHz，經由模擬結果得知，信號轉換的時間，最大可量測的時間為44.8ns ，時間的解析度為12.44ps。

In the present work, we propose the idea of using vernier ring delay line (VDL) with to develop a 13 bit two stage time to digital converter. The converter is based on the fundamental method of counting the full clock cycles of a low-phase-noise reference clock. The use of vernier ring delay line technique significantly relaxes the device matching requirement than vernier delay line (VDL) and also reduces the chip area. Simulation results showed that the time resolution is around 12.44ps and the full input range is about is 44.8ns.
The present work is designed using 0.18um CMOS process. Simulation result shows that the overall time resolution of the TDC is 12.44ps,the full input range is about 44.8ns. Besides,respectively.

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