我們提出了一個省電導向的正反器合併以及重新擺放的方法，這個方法應用在傳統時間導向的擺放之後，以及時脈網絡合成之前。我們的目的是希望能夠藉由縮減時脈網絡的大小來減少電能的消耗量，另外一個目的是減少連結到正反器的訊號切換，所需要消耗的能量。同時我們也需要考慮到合併過後的多位元正反器在合併後是否能夠擺放到符合時間限制的區域內，以及在擺放的時候同時避免擺放的過度密集。我們的實驗結果非常好，執行了許多測試資料後，我們的方法在經過邏輯閘氏時脈網絡合成之後，可以減少時脈網絡鎖消耗的電能達到38至46個百分比。同時也可以縮減連結到正反器的訊號切換，所需要消耗的能量大約7到42個百分比。

We propose a power-driven flip-flop merging and relocation approach that can be applied after conventional timing-driven placement and before clock network synthesis. It targets to reduce the clock network size and thus the clock power consumption, as well as the switching power of the nets connected to the flip-flops by selectively merging flip-flops into multi-bit flip-flops and relocating them under timing and placement density constraints. The experimental results are very encouraging. For a set of benchmarks, our approach reduced the switching capacitance of clock network by 38 to 46% after gated clock tree synthesis. Meanwhile, the switching power of signal nets connected to the flip-flops were reduced by 7 to 42%.

[1] D. Liu and C. Svensson. Power consumption estimation in CMOS VLSI chips. IEEE Solid-State Circuits, 29:663–670, 1994.
[2] K.Wang and M.Marek-Sadowska. Buffer sizing for clock power minimization subject to general skew constraints. In Design Automation Conference, pages 153–156, 2004.
[3] G. Wilke and R. Reis. A new clock mesh buffer sizing methodology for skew and power reduction. In IEEE Computer Society Annual Symposium on VLSI, pages 227–232, 2008.
[4] A.S. Seyedi, S.H. Rasouli, A. Amirabadi, and A. Afzali-Kusha. Low power low leakage clock gated static pulsed flip-flop. In IEEE International Symposium on Circuits and Systems, pages 3658–3611, 2006.
[5] S. Naik and R. Chandel. Design of a low power flip-flop using cmos deep sub micron technology. In International Conference on Recent Trends in Information, Telecommunication and Computing, pages 253–256, 2010.
[6] C.C. Yu. Design of low-power double edge-triggered flip-flop circuit. In IEEE Conference on Industrial Electronics and Applications, pages 2054–2057, 2007.
[7] S.K. Teng and N. Soin. Low power clock gates optimization for clock tree distribution. In International Symposium on Quality Electronic Design, pages 488–492, 2010.
[8] M. Donno, A. Ivaldi, L. Benini, and E. Macii. Clock-tree power optimization based on RTL clock-gating. In Design Automation Conference, pages 622–627, 2003.
[9] Q. Wu, M. Pedram, and X. Wu. Clock-gating and its application to low power design of sequential circuits. IEEE Transactions on Circuits Systems I, 47(3):415–420, 2000.
[10] Y. Cheon, P.H. Ho, A.B. Kahng, S. Reda, and Q. Wang. Power-aware placement. In Design Automation Conference, pages 795–800, 2005.
[7] S.K. Teng and N. Soin. Low power clock gates optimization for clock tree distribution. In International Symposium on Quality Electronic Design, pages 488–492, 2010.
[8] M. Donno, A. Ivaldi, L. Benini, and E. Macii. Clock-tree power optimization based on RTL clock-gating. In Design Automation Conference, pages 622–627, 2003.
[9] Q. Wu, M. Pedram, and X. Wu. Clock-gating and its application to low power design of sequential circuits. IEEE Transactions on Circuits Systems I, 47(3):415–420, 2000.
[10] Y. Cheon, P.H. Ho, A.B. Kahng, S. Reda, and Q. Wang. Power-aware placement. In Design Automation Conference, pages 795–800, 2005.
[11] Y. Lua, C.N. Sze, X. Hong, Q. Zhou, Y. Cai, L. Huang, and J. Hu. Navigating registers
in placement for clock networkminimization. In Design Automation Conference, pages 176–181, 2005.
[12] W. Hou, D. Liu, and P.H. Ho. Automatic register banking for low-power clock trees. In International Symposium on Quality Electronic Design, pages 647–652, 2009.
[13] R.P. Pokala, R.A. Feretich, and R.W. McGuffin. Physical synthesis for performance optimization. In IEEE International ASIC Conference and Exhibit, 1992.
[14] Y. Kretchmer. Using multi-bit register inference to save area and power: the good, the bad, and the ugly. In EE Times Asia, 2001.
[15] Y.T. Chang, C.C. Hsu, P.H. Lin, Y.W. Tsai, and S.F. Chen. Post-placement power optimization with multi-bit flip-flops. In IEEE/ACM International Conference on Computer-Aided Design, 2010.
[16] C.L. Chang, Iris H.R. Jiang, Y.M. Yang, Evan Y.WTsai and Lancer S.F. Chen INTEGRA: Fast Multi-Bit Flip-Flop Clustering for Clock Power Saving Based on Interval Graphs In International Symposium on Physical Design, 2011
[17] G. Chabert, L. Jaulin, and X. Lorca. A constraint on the number of distinct vectors with application to localization. Technical report, Small workshop on IntervalMethods, 2009.
[18] U. Brenner and J. Vygen. Legalizing a placement with minimum total movement. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pages 1597–1613, 2004.
[19] S. Chou and T.Y. Ho. OAL: An obstacle-aware legalization in standard cell placement with displacement minimization. In IEEE International SOC Conference, pages 329–332, 2009.
[20] H. Imai and T. Asano Finding the connected components and a maximum clique of an intersection graph of rectangles in the plane. Journal of Algoritms, vol. 4, issue 4, pages 310-323.
[21] M.I. Shamos and D. Hoey. Geometric intersection problems. In IEEE Symposium on Foundations of Computer Science, 1991.
[22] T.H. Cormen, C.E. Leiserson, and C. Stein Introduction to algorithms 2/e, page 194.
[23] M. Matsumoto. and T. Nishimura. Mersenne twister: a 623-dimensionally equidistributed uniform pseudo-random number generator. ACM Transactions on Modeling and Computer Simulation, vol 8(1), pages 3–30, 1998
[24] H. Abelson, J. Sussman, and J. Sussman. Structure and Interpretation of Computer Programs. MIT, 1984.
[25] CAD contest of Taiwan. http://cad_contest.ee.ntu.edu.tw/cad10/
Problems/B1_Faraday_091223_MultiBitFF.pdf
[26] R.S. Tsay. Exact zero skew. In IEEE International Conference on Computer-Aided Design, pages 336–339, 1991.
[27] S.H. Wang, Y.Y. Liang, T.Y. Kuo, and W.K. Mak. Power-Driven Flip-Flop Merging and Relocation. In International Symposium on Physical Design, pages 107–114, 2011.
[28] W.C. Chao andW.K.Mak. Low-Power Gated and Buffered Clock Network Construction. Transactions on Design Automation of Electronic Systems, vol 13(1), 2008.
[29] J. Oh and M. Pedram. Gated clock routing for low-power microprocessor design. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol 20(6), pages 715–722, 2001.