磁性隨機存取記憶體的寫入干擾錯誤模型及其測試與診斷方法

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研究生：	蔡志偉 Chih-Wea Tsai
論文名稱：	磁性隨機存取記憶體的寫入干擾錯誤模型及其測試與診斷方法 MRAM Write Disturbance Fault Modeling, Testing, and Diagnosis
指導教授：	吳誠文 Cheng-Wen Wu
口試委員:
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2006
畢業學年度：	94
語文別：	中文
論文頁數：	76
中文關鍵詞：	磁性隨機存取記憶體、干擾錯誤、錯誤模型、記憶體、測試、診斷
外文關鍵詞：	MRAM, Disturbance Fault, Fault Model, Memory, Testing, Diagnosis
相關次數：	點閱：1 下載：0
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　　磁性隨機存取記憶體（MRAM）被視為在未來具有潛力可以取代現有的靜態隨機存取記憶體（SRAM）、動態隨機存取記憶體（DRAM）及快閃記憶體（Flash memory）等等內嵌式和商用式記憶體。它同時具備了隨機存取記憶體及快閃記憶體的優點，所以在未來很有可能會被廣泛地應用在系統晶片（System-On-Chip）上。近幾年來，有一些磁性隨機存取記憶體產品在市場上出現，但並不表示其測試相關問題已被解決。

　　為了確保磁性隨機存取記憶體產品的品質及良率，藉由實際晶片的量測結果，本論文針對該記憶體提出了「寫入干擾錯誤模型（Write Disturbance Fault Model）」。同時也發展出一個稱作RAMSES-M的磁性隨機存取記憶體的錯誤模擬程式，利用它來推導寫入干擾錯誤模型的最短測試演算法。並且為了找出寫入干擾錯誤的錯誤原因及其程度，我們亦提出一「可適應診斷演算法（Adaptive Diagnosis Algorithm）」來進行錯誤診斷。藉由工研院電子所提供的磁性穿隧接面（Magnetic Tunneling Junction）元件模型，我們也建立了「翻轉式磁性隨機存取記憶體（Toggle MRAM）」陣列的SPICE電路模型，以獲得寫入干擾錯誤模型及其診斷方法的電路模擬結果。最後，本論文也提出了一個具有寫入干擾錯誤診斷能力的「磁性隨機存取記憶體內建式自我測試電路（MRAM Built-In Self-Test Circuit）」；同時利用翻轉式磁性隨機存取記憶體的「寫入前先讀（Read-before-Write）」寫入機制，我們亦提出一個特殊的內建式自我測試電路實現方法，可以用來縮短整體的測試時間。

　　電路模擬及RAMSES-M程式模擬結果均顯示March C-測試演算法能夠偵測出寫入干擾錯誤，而且March-17N diagnosis可以區分出寫入干擾錯誤和傳統的錯誤模型。同時電路模擬結果亦証明了「可適應診斷演算法」足以用來診斷寫入干擾錯誤。而針對1-Mbit磁性隨機存取記憶體所提出的內建式自我測試電路之硬體面積只佔該記憶體的0.75%；若再針對翻轉式磁性隨機存取記憶體，將此測試電路整合「寫入前先讀」之機制，則可大幅地縮短所需的測試時間。

The Magnetic Random Access Memory (MRAM) is considered one of the potential candidates that will replace current on-chip and commodity memories (SRAM, DRAM, and flash memory) in the future. MRAM combines advantages of RAM and flash memory, making it a potential choice for system-on-chip (SOC). There are few MRAM products on the market presently, but this does not imply the test issues of MRAM are solved.

For assuring the quality and yield of MRAM, we present the Write Disturbance Fault (WDF) model for MRAM, which is justified by chip measurement results. We also present an MRAM fault simulator called RAMSES-M, based on which we derive the shortest test for the proposed WDF model. To identify WDF, an Adaptive Diagnosis Algorithm (ADA) is developed for fault diagnosis. We also construct the SPICE model of toggle MRAM array from the magnetic tunneling junction (MTJ) device model of ERSO* to obtain circuit simulation results for WDF testing and diagnosis. Finally, we design an MRAM BIST circuit with WDF diagnosis capability, and a particular BIST implementation method which utilizes the Read-before-Write mechanism is proposed to reduce overall test time.

The experimental results from circuit simulation and RAMSES-M show that the March C- test algorithm detects WDF, and March-17N diagnosis algorithm distinguishes the WDF from conventional faults. Also, circuit simulation result justifies that the adaptive diagnosis algorithm is useful for diagnosis of a WDF cell. Finally, BIST circuit has only 0:75 % of hardware overhead for a 1-Mbit MRAM, and test time is further shortened for the toggle MRAM.

*Electronics Research and Service Organization, Industrial Technology Research Institute, Taiwan

Abstract i
Introduction 1
1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2 Proposed Fault Model and Testing Method . . . . . . . . . . . . . . . . . . . . . . 2
3 ThesisOrganization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Magnetic Random Access Memory (MRAM) 4
1 OverviewofMRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.1 AsteroidMRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2 Toggle MRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 CellStructure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3 MTJMaterial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4 BasicOperations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.1 WriteOperation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.2 ReadOperation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Write Disturbance Fault Model 10
1 MagneticField ImpactonMRAMOperation . . . . . . . . . . . . . . . . . . . . 10
2 WriteDisturbanceFault (WDF)Model . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1 Shift ofOperatingRegion . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2 Proposed Fault Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3 TestingforWriteDisturbanceFault . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1 FaultActivationandDetection . . . . . . . . . . . . . . . . . . . . . . . . 15
3.2 ShortestTestingMethod . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.3 MRAMFaultSimulator: RAMSES-M. . . . . . . . . . . . . . . . . . . . 16
Diagnosis forWrite Disturbance Fault 18
1 Purpose of WDF Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2 Influence of Different Shift Amount . . . . . . . . . . . . . . . . . . . . . . . . . 18
3 Adaptive Diagnosis Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.1 Phase 1:DetectionPhase . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.2 Phase 2: CurrentScanPhase . . . . . . . . . . . . . . . . . . . . . . . . . 22
4 CostAnalysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.1 TraditionalMethod . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.2 Proposed Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Circuit Simulation of MRAM 29
1 SPICEModelofMRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
1.1 MTJCellModeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
1.2 MemoryArrayModeling . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
1.3 MagneticFieldDisturbanceModeling . . . . . . . . . . . . . . . . . . . . 33
1.4 Defect Injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2 SimulationofFaultyMRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2.1 SimulationforWDF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2.2 Simulation for WDF Diagnosis . . . . . . . . . . . . . . . . . . . . . . . 36
Built-In Self-Test Design 37
1 TargetedMemoryDescription . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
1.1 MemorySpecification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
1.2 Toggle MRAM Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
2 BISTSpecification andArchitecture . . . . . . . . . . . . . . . . . . . . . . . . . 38
2.1 BISTSpecification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.2 BISTArchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3 WDF Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.1 Diagnosis Scheme and Flow . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.2 Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.3 Sequencer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.4 TestPatternGenerator . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4 TestTimeReduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
4.1 Utilization of Read-before-Write Mechanism . . . . . . . . . . . . . . . . 52
4.2 ImplementationMethod . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Experimental Results 56
1 SPICESimulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
1.1 SimulationResultofWDF . . . . . . . . . . . . . . . . . . . . . . . . . . 56
1.2 Simulation Result of WDF Diagnosis . . . . . . . . . . . . . . . . . . . . 62
2 RAMSES-M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
3 BIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
3.1 WDF Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
3.2 TestTimeReduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Conclusion and Future Work 70
1 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
2 FutureWork . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

                                

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