本研究為設計一個兩級游標尺延遲線之時間數位轉換器，解決單級游標尺延遲線會發生信號轉換時間過長的問題，同時減少元件數目。介於兩個脈衝信號之間的待測時間，經由控制電路分解為參考時脈週期的整數倍及非整數倍兩部份，整數倍交由計數器計算，非整數倍則送到兩級游標尺延遲線。由第一級游標尺延遲線得到較粗略的解析度（Tclk / 14），再將處理過的信號經由本研究所設計之新架構的介面電路傳送到第二級游標尺延遲線得到更精確的解析（Tclk / 196），最後由讀出電路將溫度計碼型式的輸出轉為二進位型式的輸出並做減法的運算，得到最後的結果。游標尺延遲線所使用的延遲元件由延線鎖相迴路來控制其偏壓，使得延遲元件能夠穩定提供電路所需的兩種延遲時間：Tclk / 14及Tclk．15 / 196。
　　電路使用的製程是TSMC CMOS 0.18um 1P6M，由延遲元件之延遲時間、信號轉換時間及誤差分析的考量，選擇參考時脈的頻率為200MHz。經由模擬結果得知，信號轉換的時間小於5個參考時脈週期，最大可量測的時間為75ns。在時間的解析度修正為29.6ps的情形下，DNL介於-0.33LSB ~ +0.69LSB，INL介於+0.47LSB ~ -1.08LSB。

This paper describes the design of time-to-digital converter with two level Vernier delay line（VDL）, which is used to solve the problem of long conversion time in single level VDL and reduce the elements. The time to be measured between two pulse signals is separated into integral period part and non-integral period parts by control circuit. Integral part is sent into counter, and non-integral parts are sent into the two level VDL. In the first VDL can get coarse resolution（Tclk/14）, and the signals will be transferred to the second VDL by the new structure interface circuit. Fine resolution（Tclk/196）can be gotten in the second VDL. Finally, readout circuit converts thermal code to binary code and do the subtraction to get the final results. The bias voltages of delay elements in VDL are controlled by DLL, this makes delay elements can stably provide two delay time：Tclk / 14 and Tclk．15 / 196.
The circuit uses the process of TSMC CMOS 0.18um 1P6M. 200Mhz clock frequency is chosen by the consideration of delay time, conversion time, and error analysis. From the simulation results, the conversion time is smaller than 5 clock periods, the maximum time can be measured is 75ns. After the fine resolution is modified to 29.6ps, the DNL is within -0.33LSB ~ +0.69LSB，and INL is within +0.47LSB ~ +1.08LSB.

[ 1] J. Christiansen, “An Integrated CMOS 0.15 ns Digital Timing Generator for TDC’s and Clock Distribution Systems,” IEEE Transactions on Nuclear Science, vol. 42, Aug. 1995.
[ 2] E. Raisanen-Ruotsalainen, T. Rahkonen, J. Kostamovaara, “A Low-Power CMOS Time-to-Digital Converter,” IEEE Journal of Solid-State Circuits, vol. 30, pp. 984-990, Sept. 1995.
[ 3] K. Maatta, J. Kostamovaara, “A High-Precision Time-to-Digital Converter for Pulsed Time-of-Flight Laser Radar Applications,” IEEE Transactions on Instrumentation and Measurement, vol. 47, No. 2 , April 1998.
[ 4] E. Raisanen-Ruotsalainen, T. Rahkonen, J. Kostamovaara, “An Integrated Time-to-Digital Cnverter with 30-ps Single-Shot Precision,” IEEE Journal of Solid-State Circuits, vol. 35, No. 10, Oct. 2000.
[ 5] E. Raisanen-Ruotsalainen, T. Rahkonen, J. Kostamovaara, “A Time Digitizer with Interpolation Based on Time-to-Voltage Conversion,” Proceedings of the 40th Midwest Symposium on Circuits and Systems, Vol. 1, pp. 197-200, Aug. 1997.
[ 6] Y. Arai, T. Ohsugi, “TMC-a CMOS Time to Digital Converter VLSI,” IEEE Transactions on Nuclear Science, vol. 36, No. 1, Feb. 1989.
[ 7] M.S. Gorbics, J. Kelly, K.M. Roberts, R.L. Sumner, “A High Resolution Multihit Time to Digital Converter Integrated Circuit,” IEEE Conference Record. Nuclear Science Symposium, vol. 1 , pp. 421-425, Nov. 1996.
[ 8] P. Dudek, S. Szczepanski, J.V. Hatfield, “A High-Resolution CMOS Time-to-Digital Converter Utilizing a Vernier Delay Line,” IEEE Journal of Solid-State Circuits, vol. 35, No. 2, Feb. 2000.
[ 9] Chorng-Sii Hwang, Poki Chen, Hen-Wai Tsao, “A High-Precision Time-to-Digital Converter Using a Two-Level Conversion Scheme,”
[10] Chorng-Sii Hwang, Poki Chen, Hen-Wai Tsao, “A High-Resolution and Fast-Conversion Time-to-Digital Converter,” Proceedings of the 2003 International Symposium on Circuits and Systems, vol. 1, pp. 25-28, May 2003.
[11] Poki Chen, Shepz-Iuan Liu, Jingshown Wu, “A Low Power High Accuracy CMOS Time-to-Digital Converter,” IEEE International Symposium on Circuits and Systems, vol. 1, pp. 281-284, June 1997.
[12] Poki Chen, Shen-Iuan Liu, “A Cyclic CMOS Time-to-Digital Converter With Deep Sub-nanosecond Resolution,” Proceedings of the IEEE 1999 Custom Integrated Circuits, pp. 605-608, May 1999.
[13] C. T. Gray, W. Liu, W.A. M. Van Niije, T. A. Hughes Jr., and R. K. Cavin III, “A sampling technique and its CMOS implementation with 1Gb/s bandwidth and 25 ps resolution,” IEEE Journal of Solid-State Circuits, vol. 29, pp. 340-349, Mar. 1994.
[14] Uming Ko, P.T. Balsara, “High Performance, Energy Efficient Master-Slave Flip-Flop Circuits,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 8, No. 1, pp. 94-98, Feb. 2000.
[15] Sngn-Mo Kang, Yusuf Leblebigi, “CMOS Digital Integrated Circuits Analysis and Design,” McGraw-Hill, 2nd edition, 1999.
[16] Daniel D. Gajski, “Principles of Digital Design,” Prentice-Hall, 2nd edition, 1997.
[17] Behard Razavi, “Phase-Locking in High-Performance Systems From Devices to Architectures,” IEEE PRESS, pp. 17-18, 2003.
[18] N.R. Mahapatra, S.V. Garimella, A. Tareen, “ An Empirical and Analytical Comparison of Delay elements and A New Delay Element Design,” Proceedings of IEEE Computer Society Workshop on VLSI, pp. 81-86, April 2000.
[19] A. Mantyniemi, T. Rahkonen, J. Kostamovaara, “A High Resolution Digital CMOS Time-to-Digital Converter Based on Nested Delay Locked Loops,” Proceedings of IEEE International Symposium on Circuits and Systems, vol. 2, June 1999.
[20] M. Maymandi-Nejad, M. Sachdev, “A Digitally Programmable Delay Element : Design and Analysis,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 11, No. 5, October 2003.
[21] D.M. Santos, S.F. Dow, J.M. Flasck, M.E. Levi, “A CMOS Delay Locked Loop And Sub-Nanosecond Time-to-Digital Converter Chip,” IEEE Transactions on Nuclear Science, vol. 43, No. 3, June 1996.
[22] CIC, “Nyquist-Rate A/D Converter Design Training Manual,” CIC, July 2003.