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研究生： 黃昱彰
Huang, Yu-Chang
論文名稱： 藉由重複利用運算結果及提升資源利用率來加速實現於終端設備上的二值化神經網路推論的研究
Accelerating Binarized Neural Network Inference by Reusing Operation Results and Elevating Resource Utilization on Edge devices
指導教授： 王俊堯
Wang, Chun-Yao
口試委員: 陳勇志
Chen, Yung-Chih
陳聿廣
Chen, Yu-Guang
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 資訊工程學系
Computer Science
論文出版年： 2022
畢業學年度： 110
語文別： 英文
論文頁數： 20
中文關鍵詞： 二值化神經網路 、現場可程式化邏輯閘陣列 、加速器
外文關鍵詞： Binarized neural network (BNNs), FPGA, Accelerator
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    • 近年來卷積式神經網路已在電腦視覺，如自駕車及影像辨識等領域，展現其出色的能力。然而，龐大的運算量、功耗及記憶體需求，仍然是其應用在終端設備時所需面臨的挑戰。針對這個問題，一個可行的方法便是利用二值化神經網路。近期的研究已經證明二值化神經網路能夠在可接受的精確度損失下顯著地降低運算複雜度及記憶體需求。在此篇論文中，我們提出了一種用於二值化神經網路推論的加速器設計。該設計大幅減少所需的運算量並提升了終端設備上的資源利用率。

    Convolutional Neural Networks (CNNs) have shown their abilities in computer vision such as self-driving car and image classification applications. However, computation, power consumption, and memory requirement remain challenges for CNNs when applied in the domains of edge devices. To address these challenges, one of the possible solutions is using Binarized Neural Networks (BNNs). Researchers have demonstrated that BNN models dramatically reduce computational complexity and memory requirements with acceptable accuracy loss. This paper presents an accelerator design for BNN inference that minimizes the number of operations and elevates resource utilization on edge devices. We implemented our accelerator on the Xilinx ZCU104 FPGA and evaluated it with TFC, CNV and VGG-13 like BNN networks for MNIST, CIFAR-10 and Tiny ImageNet. Experimental results show that our accelerator can reduce, on average, 99.2\% operations and achieve up to 1974 speedup on an FPGA platform compared to state-of-the-art design.

    中文摘要-----------------------------------------i Abstract----------------------------------------ii Acknowledgement---------------------------------iii Contents----------------------------------------v List of Tables----------------------------------vii List of Figures---------------------------------viii 1 Introduction----------------------------------1 2 Background------------------------------------3 2.1 Convolutional Neural Networks---------------3 2.2 Binarized Neural Networks-------------------4 3 Proposed Framework----------------------------6 3.1 Multiplexer-based Similarity Operation------6 3.2 Average Redundancy Rate---------------------8 3.3 Accumulation Controller---------------------9 3.4 Pruning Comparator--------------------------11 3.5 Overall Architecture------------------------11 4 Experimental Results--------------------------13 5 Conclusion------------------------------------18

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