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研究生: 林志豪
Lin, Chih-Hao
論文名稱: 具有雙模式操作可應用於可見光通訊之互補式金氧半導體影像感測器
A Dual-Mode CMOS Image Sensor for Visible Light Communication
指導教授: 謝志成
Hsieh, Chih-Cheng
口試委員: 陳新
鄭桂忠
邱進峯
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年: 2014
畢業學年度: 103
語文別: 英文
論文頁數: 99
中文關鍵詞: 影像感測器光通訊光接收器雙模式可見光通訊
外文關鍵詞: image sensor, optical communicatiom, optical receiver, dual-mode, visible light communication
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  • 本論文描述了一個適合應用於可見光通訊之雙模式操作互補式金氧半導體影像感測器。此影像感測器之雙模式操作為影像模式及通訊模式。此論文貢獻了許多創新之處,首先是提出了可提供雙模式操作之四個電晶體的畫素架構。第二為提出一個在通訊模式下可以消除不必要的背景資訊以及避免壓縮輸出電壓容許空間之背景消除技術。第三為提出一個可程式化陣列面積之光感應電流相加方式來增加光感度,而此陣列面積則由所提出之即時追蹤光源功能來決定。
    此操作電壓為3.3伏特之雙模式操作互補式金氧半導體影像感測器晶片使用n+/p-sub 感光二極體的64 × 64畫素陣列,每畫素包含四個電晶體,其畫素大小為 10 × 10 um2,填充因子為54.9%,並以TSMC 0.18μm CMOS 1P6M 標準製程製作。本影像感測器晶片的量測結果於影像模式下具1.3V /lux•s感光度之原始影像資訊輸出;於通訊模式下透過所提出之電流相加特性具有1倍至64倍之可調增益光感度,而此光接受器之最佳頻寬為1MHz,位元錯誤率為10-9。
    改良式雙模式操作互補式金氧半導體影像感測器晶片使用64 × 64畫素陣列,每畫素包含四個電晶體,其畫素大小為 7.6 × 7.6 um2,填充因子為45%,操作電壓為3.3伏特,並以TSMC 0.18μm CMOS 1P6M 標準製程製作。本改良式影像感測器晶片的量測結果於影像模式下具1.136V /lux•s感光度及每秒120張影像輸出,功率消耗為1.093mW;於通訊模式下具有每秒5000張資訊輸出之即時追蹤功能,並且在一可靠之背景消除技術之下此光接受器之最佳頻寬為6MHz,位元錯誤率為3.8×10-6。


    This thesis presents a dual-mode CMOS image sensor suitable for visible light communication. The dual-mode operation of the proposed imager is image mode and communication mode. There are several innovations in this thesis. First, a compact four transistors pixel structure provides the dual-mode operation. Second, a background cancelling function in communication mode can eliminate the undesired background information and avoid suppressing the output voltage headroom. Third, photo-sensing current summation scheme with a programmable array area is implemented to improve the photo-sensitivity, where the array area is defined by the proposed real-time light source tracking function.
    The prototype dual-mode CMOS imager chip consisting of 64 × 64 4-T pixel array with n+/p-sub photodiode and pixel pitch as 10 × 10 μm2 with 54.9% fill factor and 3.3V operation has been designed and fabricated in TSMC 0.18μm CMOS 1P6M standard process. The measured results achieve raw image data output in image mode with 1.3V/lux•s sensitivity, and real-time output in communication mode with tunable gain of photo-sensitivity from ×1 to ×64 by proposed current summation feature and maximum receiver bandwidth of 1MHz with 10-9 bit-error rate, respectively.
    The revised dual-mode CMOS imager chip consisting of 64 × 64 4-T pixel array and pixel pitch as 7.6 × 7.6 μm2 with 45% fill factor and 3.3V operation has been designed and fabricated in TSMC 0.18μm CMOS 1P6M standard process. In image mode, the measured results achieve 1.136V/lux•s sensitivity at 120 fps with 1.093mW power consumption. In communication mode, the measured results achieve a real-time tracking with 5000fps tracking rate and maximum receiver bandwidth of 6MHz with 3.8×10-9 bit-error rate with a reliable background cancelling function.

    摘要 I ABSTRACT II CONTENTS III LIST OF FIGURES VI LIST OF TABLES X CHAPTER 1 INTRODUCTION 1 1.1 MOTIVATION 1 1.2 THESIS CONTRIBUTION 2 1.3 THESIS ORGANIZATION 4 CHAPTER 2 BACKGROUND INFORMATION 5 2.1 REVIEW OF THE IMAGE SENSOR 6 2.1.1 System Architecture 6 2.1.2 Active Pixel Sensor 7 2.1.3 Basic Sensor Characteristics 8 2.1.4 Correlated Double Samplings (CDS) 10 2.2 REVIEW OF THE OPTICAL RECEIVER 11 2.2.1 System Architecture 11 2.2.2 Trans-impedance Amplifier (TIA) 12 2.2.2.1 Open-loop TIA 13 2.2.2.2 Feedback TIA 14 2.2.3 Basic TIA Characteristics 14 2.3 DESIGN CONSIDERATION OF THIS WORK AND SUMMARY 16 2.4.1 In-Pixel Devices 17 2.4.2 Communication Bandwidth 17 2.4.3 Summary 17 CHAPTER 3 3-T APS BASED DUAL-MODE IMAGER FOR IMAGE SENSOR COMMUNICATION 18 3.1 CONCEPT OF DUAL-MODE OPERATION 18 3.1.1 Image Mode Readout Scheme 19 3.1.2 Communication Mode with Current Summation Function Readout Scheme 20 3.2 CHIP IMPLEMENTATION 21 3.2.1 System Architecture 21 3.2.2 Pixel structure 23 3.2.3 Correlated Double Sample (CDS) 26 3.2.4 Trans-impedance Amplifier (TIA) 32 3.2.5. Column and Row Selects 36 3.2.6. Digital Control Circuit 37 3.3 ANALYSIS OF COMMUNICATION MODE 39 3.4 CHIP OPERATION IN IMAGE MODE 41 3.5 SUMMARY 42 CHAPTER 4 REVISED DUAL-MODE IMAGER WITH LIGHT SOURCE TRACKING AND BACKGROUND CANCELLING 43 4.1 OPERATION CONCEPT 44 4.1.1 Light Source Tracking 44 4.1.2 Background Cancelling 45 4.1.3 Current Buffer 47 4.2 CHIP IMPLEMENTATION 47 4.2.1 System Architecture 47 4.2.2 Current Comparator 49 4.2.3 Buffered Direct Injection 53 4.2.4 TIA with Background Current Control 55 4.2.5 Addressing 59 4.2.6 Column and Row Selects 60 4.3 ANALYSIS OF COMMUNICATION MODE 61 4.4 CHIP OPERATION IN IMAGE MODE 63 4.5 SUMMARY 64 CHAPTER 5 MEASUREMENT RESULTS 65 5.1 MEASUREMENT ENVIRONMENT SETUP 65 5.2 3T-APS BASED DUAL-MODE IMAGER FOR VISIBLE LIGHT COMMUNICATION 67 5.2.1 Imager Chip 67 5.2.2 Image Mode Measurement 70 5.2.2.1. Transfer Curve 70 5.2.2.2. Sample Images 71 5.2.3 Communication Mode Measurement 72 5.2.3.1. Real-Time Output 72 5.2.3.2. Current Summation 72 5.2.3.3. Frequency Response 73 5.2.3.4. Bit Error Rate 75 5.2.3.5. Communication Demo 76 5.3 REVISED DUAL-MODE IMAGER WITH LIGHT SOURCE TRACKING AND BACKGROUND CANCELLING 78 5.3.1 Imager Chip 78 5.3.2 Image Mode Measurement 80 5.3.2.1. Transfer Curve 80 5.3.2.2. Sample Images 80 5.3.3 Communication Mode Measurement 82 5.3.3.1 Light Source Tracking 82 5.3.3.2 Background Cancelling 87 5.3.3.3 Frequency Response 87 5.3.3.4 Bit Error Rate 88 5.4 SUMMARY 89 CHAPTER 6 CONCLUSION AND FUTURE WORK 92 6.1. CONCLUSION 92 6.2. FUTURE WORK 94 BIBLIOGRAPHY 95

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