在全球半導體業越來越激烈的競爭之下，半導體廠必須藉由良率提升、生產力提升以及成本降低以維持競爭優勢。隨著尺寸的緊縮與積體電路技術進入至奈米世代，越來越複雜的製造過程也導致產品的低良率。然而，低良率的問題難藉由改善製造過程而完全解決，其中有大部分必須藉由改善積體電路之設計從源頭做起。設計者必須具備晶圓製造相關的領域知識，以確認積體電路設計因子與製造反應因子的因果關係。然而，設計者往往並非製造上的專家，有些關係並無法直接透過物理關係或複雜的數學方程式架構。在晶片設計與晶圓製造的過程中均會產生與紀錄大量的資料，而這些資料中可能隱含著有意義的資訊。本研究目的係提出一可製造性設計之資料挖礦架構，利用資料挖礦方法建構設計因子與製造反應因子之因果關係，作為晶片佈局之設計指導規則基礎，以獲得較佳之可製造性。所萃取之樣型或歸納之規則更可進一步作為設計者驗證其假設或提供設計改善方向。本研究藉由晶圓生產力提升與良率提升之實證研究以驗證本架構之效度與實際可行性。研究結果發現本研究架構可協助晶片設計者取得較佳之晶片佈局設計，以提升晶圓生產力，並且提供一套指導原則，在考慮量測成本與補償成效下，建議設計者規劃量測覆蓋誤差之佈局，以提升曝光之良率。

As global competition continues to strengthen in semiconductor industry, semiconductor companies strive to maintain competitive advantages through yield enhancement, productivity improvement, and cost reduction. As the shrinking feature size and the advanced technology of integrated circuit (IC), the impact of unpredictable variations of manufacturing process are increasing and leading to low yield. The low yield problem can hardly be solved by manufacturing process improvement alone, while it can be improved by design of chip modification. In particular, cause-and-effect relationship between IC designable variables and manufacturing response variables should be identified in advance. However, some of them cannot be formulated directly by physical or mathematical formula. In particular, amounts of data have been recorded during design and manufacturing process, yet meaningful information is latent behind the huge data. This study aims to develop a data mining framework of design for manufacturability (DFM), in which data mining methodology is applied to construct the casual relation as the basis of design guidelines to improve chip layout with better manufacturability. The extracted patterns or derived rules can not only help designer to validate the assumption of design variable but also be a basis of further improvement direction. Finally, two empirical studies for enhancing wafer productivity and yield were conducted to evaluate the validity of proposed framework and practical viability. The proposed framework can assist IC designer in effectively deriving chip layout design for wafer productivity enhancement. In addition, it also can provide a guideline of overlay registration layout for exposure yield enhancement with metrology cost and compensation performance taken into account.

Allan, G. A., Walton, A. J., and Holwill, R. J. (1992), “An yield improvement technique for IC layout using local design rules,” IEEE Transactions on Semiconductor Manufacturing, Vol. 11, No. 11, pp. 1355-1362.
Anderson, D. M. (1990), Design for Manufacturability, Optimizing Cost, Quality, and Time to Market, CIM Press.
Backus, P., Janakiram, M., Mowzoon, S., Runger, G. C., and Bhargava, A. (2006), “Factory cycle-time prediction with a data-mining approach,” IEEE Transactions on Semiconductor Manufacturing, Vol. 19, No. 2, pp. 252-258.
Batista G. E. and Monard, M. C. (2003), “An analysis of four missing data treatment methods for supervised learning,” Applied Artificial Intelligence, Vol. 17, No. 5-6, pp. 519-533.
Beasley, J.E. (1985), “Algorithm for unconstrained two-dimensional guillotine cutting,” Journal of the Operational Research Society, Vol. 36, No. 4, pp. 297-306.
Berry, M., and Linoff, G. (2004), Data Mining Techniques for Marketing, Sales and Customer Support, 2nd ed., John Wiley and Sons, New York.
Bode, C.A., Ko, B.S., and Edgar, T.F. (2004), “Run-to-run control and performance monitoring of overlay in semiconductor manufacturing,” Control Engineering Practice, Vol. 12, No. 7, pp. 893-900.
Braha, D. (2001), Data Mining for Design and Manufacturing: Methods and Application, Kluwer Academic publishers.
Braha, D., and Shmilovici, A. (2002), “Data mining for improving a cleaning process in the semiconductor industry,” IEEE Transactions on Semiconductor Manufacturing, Vol. 15, No. 1, pp. 91-101.
Braha, D., and Shmilovici, A. (2003), “On the use of decision tree induction for discovery of interactions in a photolithographic process,” IEEE Transactions on Semiconductor Manufacturing, Vol. 16, No. 4, pp. 644-652.
Bralla, J. G. (1996), Design for Excellence, McGraw-Hill, Inc.
Breiman, L., Friedman, J.H., Olshen, R. J., and Stone, C.J. (1984), Classification and Regression Trees, Belmont, CA, Wadsworth.
Çakanyildirim, M., and Roundy R. (2002), “SeDFAM: semiconductor demand forecast accuracy model,” IIE Transactions, Vol. 34, No. 5, pp. 449-465.
Cano, J. R., Herrera, F., and Lozano, M. (2006), “On the combination of evolutionary algorithms and stratified strategies for training set selection in data mining,” Applied Soft Computing, Vol. 6, No. 3, pp. 323-332.
Chen, H. and Chang, C. (2001), Method to increase wafer utility by implementing deep trench in scribe line, U.S. Patent 6 214 703, April 10.
Chen, M. (2003), “Configuration of cellular manufacturing systems using association rule induction,” International Journal of Production Research, Vol. 41, No. 2, pp. 381-395
Chen, S., Chu, K., Lin, J., Tsai, C. (2007), “DFM/DFY practices during physical designs for timing, signal integrity, and power,” Asia and South Pacific Design Automation Conference 2007, pp. 232-237.
Chiang, C. and Kawa, J. (2007), Design for Manufacturability and Yield for Nano-scale CMOS, Springer, The Netherlands.
Chien, C., Chang, K., and Chen, C. (2003), “Design of sampling strategy for measuring and compensating overlay errors in semiconductor manufacturing,” International Journal of Production Research, Vol. 41, No. 11, pp. 2547-2561.
Chen, C. and Chen, L. (2007), “Using Rough Set Theory to Recruit and Retain High-Potential Talents for Semiconductor Manufacturing,” IEEE Transactions on Semiconductor Manufacturing, Vol. 20, No. 4, pp. 528-541.
Chien, C., Hsu, C., Chou, H., and Lin, C. (2006), “Overall Wafer Effectiveness (OWE): A Novel Standard for Wafer Productivity,” in Proceedings of International Symposium on Semiconductor Manufacturing Conference 2006, 25-27 September, Tokyo, Japan, pp. 317-320.
Chien, C. and Chen, L. (2008), “Data mining to improve personnel selection and enhance human capital: a case study in high-technology industry,” Expert Systems with Applications, Vol. 34, No. 1, pp. 280-290.
Chien, C., Hsiao, C., Meng, C., Hong, K., and Wang, S. (2005), “Cycle time prediction and control based on production line status and manufacturing data mining,” Proceedings of International Symposium on Semiconductor Manufacturing Conference 2005, 13-15 September, San Jose, California, USA, pp. 327-330.
Chien, C., Hsu, S., and Chen, C. (1999), “An iterative cutting procedure for determining the optimal wafer exposure pattern,” IEEE Transactions on Semiconductor Manufacturing, Vol. 12, No. 3, pp. 375-377.
Chien, C., Hsu, S., and Deng, J. (2001), “A cutting algorithm for optimizing the wafer exposure pattern,” IEEE Transactions on Semiconductor Manufacturing, Vol. 14, No. 2, pp. 157-162.
Chien, C., Hsu, S., and Hsu, C. (2007), “Enhancing competitive advantages and operational excellence for high-tech industry through data mining and digital management,” in Liao, T.W. and Triantaphyllou,Editors, Recent Advances in Data Mining of Enterprise Data: Algorithms and Applications, World Scientific, Singapore, pp. 367-410.
Chien, C. and Hsu, C. (2006), “A novel method for determining machine subgroups and backups with an empirical study for semiconductor manufacturing,” Journal of Intelligent Manufacturing, Vol. 17, No. 5, pp. 429-440.
Chien, C. and Hsu, C. (2009), “Modeling step-and-scan overlay error and unison decision analysis for sampling design for semiconductor manufacturing,” Journal of Intelligent Manufacturing (under revision).
Chien, C., Lin, D., Peng, C., and Hsu, S. (2001), “Developing data mining framework and methods for diagnosing semiconductor manufacturing defects and an empirical study of wafer acceptance test data in a wafer fab,” Journal of the Chinese Institute of Industrial Engineers, Vol. 18, No. 4, pp. 37-48.
Chien, C., Liou, C., Hsu, C., Chou, H., and Lin, C. (2007), “Optimize die size design to enhance owe for design for manufacturing,” Proceedings of International Symposium on Semiconductor Manufacturing 2007, DM-P-091.
Chien, C., and Wu, J. (2003), “Analyzing repair decisions in the site imbalance problem of semiconductor test machines,” IEEE Transactions on Semiconductor Manufacturing, Vol. 16, No. 4, pp. 704-711
Chien, C., Wang, W., and Cheng, J. (2007), “Data mining for yield enhancement in semiconductor manufacturing and an empirical study,” Expert Systems with Applications, Vol. 33, No. 1, pp. 192-198.
Cunningham, S. P., Spanos, C. J., and Voros, K. (1995), “Semiconductor yield improvement: results and best practices,” IEEE Transactions on Semiconductor Manufacturing, Vol. 8, No. 2, pp. 103-109.
Draper, N. R., and Smith, H. (1981), Applied Regression Analysis, 2nd edition, John Wiley & Sons, Inc., New York.
Famili, A., Shen, W., Weber, R, and Simoudis, E. (1997), “Data preprocessing and intelligent data analysis,” Intelligent Data Analysis, Vol. 1, No. 1-4, pp. 3-23.
Fang, L. Y., (2004) “Accelerating Firm’s Innovation through Inter-Organization: In Sectoral Innovation System Perspective,” in Proceedings of the DRUID Academy Winter 2004 PhD Conference.
Ferris-Prabhu, A. (1989), “An algebraic expression to count the number of chips on a wafer,” IEEE Circuits and Devices Magazine, pp. 37-39.
Fink, D., Sullivan, N. T., and Lekas, J. S. (1994), “Overlay sample plan optimization for the detection of higher order contributions to misalignment,” in Proceedings of SPIE: Integrated Circuit Metrology, Inspection, and Process Control VIII, Vol. 2196, pp. 389-399.
Gajski, D. D., Wu, A. C., Chaiyakul, V., Mori, S., Nukiyama, T., and Bricaud, P., (2000), “Essential issues for IP reuse,” in Proceedings of the 2000 Design Automation Conference Asia and South Pacific, 25-28 January, pp. 37-42.
Geppert, L., (1999), “Design tools for analog and digital ICs,” IEEE Spectrum, Vol. 36, No. 4, pp. 41-48.
Gerez, S. (1999), Algorithms for VLSI Design Automation, John Wiley & Sons, Inc., New York.
Han, J., and Kamber, M. (2006), Data Mining: Concepts and Techniques, 2nd ed., Morgan Kaufmann Publishers, San Francisco, CA.
Han, S., Derksen, J., and Chu, J. (2004), “Extrusion spin coating: an efficient and deterministic photoresist coating method in microlithography,” IEEE Transactions on Semiconductor Manufacturing, Vol. 17, No. 1, pp. 12-21.
Hector, S. (2006), “2005 Updates to the Lithography Chapter of the ITRS,” Lithography–2006 Electronics Manufacturing Summit.
Hifi, M. (1997), “A DH/KD algorithm: A hybrid approach for unconstrained two-dimension cutting problem,” European Journal of Operational Research, Vol. 97, No. 1, pp. 41-52.
Hsu, S., and Chien, C. (2007), “Hybrid data mining approach for pattern extraction from wafer bin map to improve yield in semiconductor manufacturing”, International Journal of Production Economics, Vol. 107, No. 1, pp. 88-103.
Hung, M., Lin, T., Cheng, F., and Lin, R. (2007), “A novel virtual metrology scheme for predicting CVD thickness in semiconductor manufacturing,” IEEE Transactions on Mechatronics, Vol. 12, No. 3, pp. 308-316.
International Technology Roadmap for Semiconductors (2005), Design, International Technology Roadmap for Semiconductors 2005 edition.
International Technology Roadmap for Semiconductors (2007), Yield Enhancement, International Technology Roadmap for Semiconductors 2007 edition.
Kahng, A. Robins, G., Singh, A., and Zelikovsky, A. (1999), “Filling algorithms and analyses for layout density control,” IEEE Transaction on Computer-Aided Design, Vol.18, No. 4, pp. 445-462.
Kotsiantis, S. B., Kanellopoulos, D. and Pintelas, P. E. (2006), “Data preprocessing for supervised learning,” International Journal of Computer Science, Vol. 1, No. 2, pp. 111-117.
Leachman, R.C., Ding, S., and Chien, C. (2007), “Economic efficiency analysis of wafer fabrication,” IEEE Transactions on Automation Science and Engineering, Vol. 4, No. 4, pp. 501-512.
Lee, R. C. T., Slagle, J. R., and Mong, C. T. (1976), “Application of clustering to estimate missing data and improve data integrity,” in Proceedings of International Conference Software Engineering, pp. 539-544.
Leenaerts, D., Gielen, G., and Rutenbar, R. A., (2001), “CAD solutions and outstanding challenges for mixed-signal and RF IC design,” in Proceedings of 2001 IEEE/ACM International Conference on Computer Aided Design, pp. 270-277.
Macher, J. T., Mowery, D. C., and Simcoe, T. S., 2002, E-Business and the semiconductor industry value chain: implication for vertical specialization and integrated semiconductor manufactures, East-West Center, Economic Series, 47.
Matheus, C. and Rendell, L. (1989), “Constructive induction on decision trees,” in Proceedings of International Joint Conference on AI, pp. 645-650.
Montgomery, D. C. (2001), Design and Analysis of Experiments, John Wiley & Sons, New York.
Moyne, J., Castillo, E. del, and Hurwitz, A. M. (2001), Run-to-run control in semiconductor manufacturing. Boca Raton, FL: CRC.
Ouyang, C., Heineken, H.T., Khare, J., Shaikh, S. and d'Abreu, M. (2000), “Maximizing wafer productivity through layout optimizations,” Thirteenth International Conference on VLSI Design, pp. 192-197.
Quinlan, J. R. (1992), “Learning with continuous classes,” in Proceedings of 5th Australian Joint Conference on Artificial Intelligence. World Scientific, Singapore, pp. 343-348.
Quinlan, J. R. (1993), C4.5: Programs for Machine Learning, Morgan Kaufmann Publishers, San Mateo CA.
Ragel, A., and Cremilleux, B. (1998), “Treatment of missing values for association rules,” In Proceedings of 2nd Pacific-Asia Conference on Knowledge Discovery and Data Mining, pp.258-270.
Raghvendra, S. and Hurat, P. (2005), “DFM: linking design and manufacturing,” Proceedings of the 18th International Conference on VLSI Design, pp. 705-708.
Raina, R. (2006), “What is DFM and DFY and why should I care?” Proceedings of International Test Conference 2006, pp. 1-9
Rangarajan, B., Templeton, M., Capodieci, L., Subramanian, R., and Scranton, A. (1998), “Optimal sampling strategies for sub-100nm overlay,” In Proceedings of SPIE: Metrology, Inspection, and Process Control for Microlithography XII, Vol. 3332, pp. 348-359.
Rumelhart, D. E., Hinton, G. E., and Williams, R. J. (1985), "Learning internal representation by error propagation", In James, L. McClelland and David E. Rumelhart, Editors, Parallel Distributed Proceeding, Vol. 1, pp. 318-362. MIT Press.
Shepherd, P. R., (1996), Integrated Circuit: Design, Fabrication and Test, McGraw Hill, New York.
Shih, W., Shih, C., and Chien, C. (2008), “Horizontal specialization and modularity in the semiconductor industry,” Harvard Business School Case Study (9-609-001).
Stoll, H.W. (1986), “Design for manufacture: An overview,” Applied Mechanic Reviews, Vol.39, No, 9, pp. 1356-1364.
Strojwas, A.J. (1989), “Design for manufacturability and yield,” in Proceedings of 26th ACM/IEEE Design Automation Conference, pp. 454-459.
Su, Y., Guo, R., and Chang, S., (2004), “Inter-firm collaboration mechanism in process development and product design between foundry and fabless design house,” in Proceedings of the 2004 Semiconductor Manufacturing Technology Workshop, pp. 47-50.
Su, Y., Guo, R., and Chang, S., (2005), “Pattern of vertical engineering collaboration between foundry and design service provider,” in Proceedings of the Fourteen IEEE International Symposium on Semiconductor Manufacturing, pp. 361-364.
Tanaka, H. (2006), Alignment mark, alignment apparatus and method, exposure apparatus, and device manufacturing method, U.S. Patent 7 006 225, February 28.
Tseng S., Wang, K., and Lee C. (2003), “A pre-processing method to deal with missing values by integrating clustering and regression techniques,” Applied Artificial Intelligence, Vol. 17, No. 5-6, pp. 535-544.
Turley, J. (2003), The Essential Guide to Semiconductors, Prentice Hall Professional Technical Reference, Upper Saddle River, NJ, USA.
Wang, Y. and Written, I. (1997), “Inducing model trees for continuous classes,” in Proceedings of Ninth European Conference Machine Learning, Someren M. van and Widmer, G., editions., pp. 128-137.
Warner, R.M. (1974), “Applying a composite model to the IC yield problem,” IEEE Journal of Solid-State Circuits, Vol. 9, No. 3, pp. 86-95.
Weber, C., Neil Berglund, C. and Gabella P. (2006), “Mask cost and profitability in photomask manufacturing: an empirical analysis,” IEEE Transactions on Semiconductor Manufacturing, Vol. 19, No. 4, pp. 465-474.
Weste, N. and Eshraghian, K. (1993), Principals of CMOS VLSI Design: a systems perspective, Addison-Wesley, Boston, USA.
Weste, N., and Harris, D. (2005), CMOS VLSI Design: a circuits and systems perspective, Addison Wesley, Boston, USA.
White, K. P., Trybula, W. J., and Athay, R.N. (1997), “Design for semiconductor manufacturing—perspective,” IEEE Transactions on Components, Packaging, and Manufacturing Technology—Pact C, Vol. 20, No. 1, pp. 58-72.
Witten, I. H. and Frank, E. (2005) Data Mining: Practical machine learning tools and techniques, 2nd Edition, Morgan Kaufmann, San Francisco, USA.
Wolf, W. (2002), Modern VLSI Design: System-on-Chip Design, 3rd edition, Prentice-Hall, PTR, Upper Saddle River, NJ, London.
Wu, J. and Hsu, C. (2009), “Critical success factors for improving decision quality on collaborative design in the IC supply chain,” Journal of Quality (forthcoming).
Wyse, N., Dubes, R., and Jain, A.K. (1980), “A critical evaluation of intrinsic dimensionality algorithms,” In Gelsema, E.S., and Kanal, L.N., editors, Pattern Recognition in Practice, pp. 415-425, Morgan Kaufmann Publishers, Inc., North-Holland, Amsterdam.
Zhang S., Zhang, C., and Yang, Q. (2003), “Data preparation for data mining,” Applied Artificial Intelligence, Vol. 17, No. 5-6, pp. 375-381.