在本論文中，我們提出了一個針對現代設計之嶄新的全域繞線演算法。我們的演算法是以反覆的重新繞線為基礎，並且提出了幾個技術來加強我們的全域繞線器。這些技術包括 (1)一個以歷史記錄為基礎的成本評估函式，其可以在反覆重新繞線階段幫助分散擁擠區域，(2)一個改良的多重起點多重終點迷宮繞行方法，其可以用來改善傳統迷宮繞行演算法的繞線長度，(3)一個辨識擁擠區域的方法來決定繞線網路的優先權，(4)一個後繞線程序，用來在以歷史記錄為基礎的反覆重新繞線已到達瓶頸時，進一步減少擁擠程度。和目前最先進的技術相比，我們的方法無論在擁擠程度或繞線長度上都表現出更佳的效能。另外在具有較大設計的ISPD07測試資料上，我們的結果的品質比起ISPD07繞線競賽所報告的最佳結果還要更好，顯示我們的演算法對於現代設計非常具有可調整性。

In this thesis, we present a new global routing algorithm for modern designs. Our algorithm is based on iterative rip-ups and reroutes, and several techniques are proposed to enhance our global router. These techniques include (1) a history based cost function which helps to distribute overflow during iterative rip-ups and reroutes, (2) an adaptive multi-source multi-sink maze routing method to improve the wirelength of maze routing, (3) a congested region identification method to specify the order for nets to be ripped up and rerouted, and (4) a post processing technique to further reduce overflow when iterative history based rip-ups and reroutes reach bottleneck. Compared with state-of-the-art works on ISPD98 benchmarks, our router outperforms them in both overflow and wirelength. For the much larger designs from the ISPD07 benchmark suite, our solution quality is better than the best results reported in the ISPD07 routing contest, showing that our algorithm is highly scalable for modern designs.

[1] R. Carden, J. Li, and C. K. Cheng, “A global router with a theoretical bound on the optimal solution,” in IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 15, pp. 208-216, 1996.
[2] C. Albrecht, “Global routing by new approximation algorithms for multicommodity flow,” in IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, pp. 622-632, 2001.
[3] R. T. Hadsell and P. H. Madden, “Improved global routing through congestion estimation,” in Proc. of Design Automation Conf., pp. 28–31, 2003.
[4] R. Kastner, E. Bozorgzadeh, and M. Sarrafzadeh, “Pattern routing: use and theory for increasing predictability and avoiding coupling,” in IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 21, pp. 777-790, 2002.
[5] Z. Cao, T. Jing, J. Xiong, Y. Hu, L. He, and X. Hong, “Dprouter: A fast and accurate dynamic-pattern-based global routing algorithm,” in Proc. Asia and South Pacific Design Automation Conf., pp. 256-261 2007.
[6] M. Pan and C. Chu, “Fastroute: A step to integrate global routing into placement,” in Proc. Int. Conf. on Computer Aided Design, pp. 464–471, 2006.
[7] M. Pan and C. Chu, “Fastroute 2.0: a high-quality and efficient global router,” in Proc. Asia and South Pacific Design Automation Conf., pp. 250-255, 2007.
[8] M. Cho and D. Z. Pan, “Boxrouter: a new global router based on box expansion and progressive ILP,” in Proc. of Design Automation Conf., pp. 373–378, 2006.
[9] D. Jariwala and J. Lillis, “Trunk decomposition based global routing optimization,” in Proc. Int. Conf. on Computer Aided Design, pp. 472-479, 2006.
[10] L. McMurchie and C. Ebeling, “Pathfinder: a negotiation-based performance-driven router for FPGAs,” in Proc. of ACM Int. Symp. on FPGAs, pp. 111–117, 1995.
[11] C. Chu and Y. Wong, “Fast and accurate rectilinear Steiner minimal tree algorithm for VLSI design,” in Proc of Int. Symp. on Physical Design, pp. 28–35, 2005.
[12] T. Lee, Congestion Constrained Layer Assignment for Via Minimization in Global Routing, Master Thesis, Department of Computer Science, National Tsing Hua University, 2007.
[13] http://www.ece.ucsb.edu/~kastner/labyrinth
[14] http://www.ispd.cc/ispd07_contest.html