在本論文中，我們擬針對如何將類循環低密度偶校碼以高效率並可靠的方式應用於快閃記憶體中之相關問題進行全面性探討。首先由理論觀點出發，進而將實務議題一併列入考量。為了能更具體化地處理問題，我們整合了當今文獻中廣泛提及的快閃記憶體錯誤機制，以數學方式提出其內部機率模型，從而計算出低密度偶校碼解碼時所需的可靠比。利用所探討的資料讀取方式搭配計算出的資料可靠比，我們提出了幾個解碼策略，它們彼此的先後順序造就了一套高效率並可靠的解碼序列，能夠做為實際快閃記憶體內部之解決方案。藉由與通訊系統間的相似性，我們也提出透過寫入已知資料來進行記憶體狀態評斷的相關方式，協助鞏固儲存資料的完整性。除此之外，對於類循環低密度偶校碼，我們也討論了一種適用於快閃記憶體規格的建構方式。利用此方式，我們建構出了一套類循環低密度偶校碼，並對其效能進行模擬及理論上的估測，最後將其應用於前述快閃記憶體的模擬當中，藉以驗證我們所提出的解碼策略確實能於快閃記憶體中發揮低密度偶校碼優異的資料保護能力。

In this work, we attempt to give a comprehensive treatment of the problem of utilizing
quasi-cyclic low-density parity-check (QC-LDPC) codes efficiently and reliably in NAND
flash memory. We start from a theoretical point of view while still take implementation
issues into account. To deal with the problem in a concrete manner, a channel model
incorporating the major sources of the threshold voltage disturbance in flash memory is
proposed from which the log-likelihood ratio (LLR) used in the decoding of LDPC codes is
mathematically derived. Based on the LLR and the investigated read techniques, we propose
several decoding strategies which constitute an efficient and reliable decoding retry sequence
that can be used as a practical solution in actual flash memory. Similar to communication
systems, pilot information and the associated scheme are discussed to mitigate performance
degradation due to the threshold voltage disturbance in memory cells. Besides decoding
strategies, a construction of QC-LDPC codes based on the additive group of a prime field
is introduced, and error-floor estimation for the constructed QC-LDPC code is provided as
well. Simulation results are presented at the end of this work to verify the effectiveness of
the proposed coding scheme and decoding retry sequence.

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