在最近的幾年內，特別是，以奈米點為基礎的金屬－絕緣體－半導體的結構不但針對它們所具有的這種新的物理現象，而且和它們的淺藏能力應用在下一個世代的單電子記憶體元件已均被廣泛的研究。利用穿襚式電子顯微鏡可以看到用電漿輔助化學氣相沉積法所長成的矽基奈米點埋藏於氮化矽薄膜中，並且可以計算其面密度大約在每平方公分1011–1012的程度。電荷被捕陷和儲存在矽基奈米點中可以顯示在室溫下的電容－電壓量測結果中，透過遲滯現象和平帶電壓的平移量在這些矽基奈米點的樣品裡。
　　在氮材料記憶體裡，我們知道有許多的深能階的缺陷陷阱在這樣的樣品中，而且在低電場下載子傳輸透過可能陷阱的幫助叫做F-P發射。在氧化矽薄膜裡，載子傳輸在高電場下如同我們知道的叫做F-N效應穿透。
　　不同於兩種不同的不連續的電何儲存中心的儲存媒介：SONOS結構中的氮陷阱和孤立的矽基奈米晶格在快閃記憶體中，矽基奈米點埋藏在氮化矽薄膜的結構在電容－電壓特性曲線中具有較大的遲滯寬度。在這一篇研究中，我們用同一種重複的電壓範圍的量測方式我們發現兩個不同機制造成的遲滯現象在同一個元件上。我們試著去分析記憶體效應和SiH4與N2的比例之間的關係，氮缺陷與矽基奈米點之間造成記憶體效應的不同。另一件事就是去研究在氮化矽薄膜中載子的傳輸機制。

In recent years, particularly, metal–insulator–semiconductor (MIS) structures based on nano-dots are widely studied for their new physical phenomena as well as their potential applications in single-electron memory devices of the next generation. Transmission electron microscopy (TEM) showed that Si NDs embedded in the silicon nitride (SiNx) thin film have been fabricated by plasma enhanced chemical vapor deposition technique, and the sheet density is the order of 1011–1012 cm-2. Charge trapping and storage in nc-Si were exhibited in capacitance–voltage (C–V) measurements at room temperature through the hysteresis and shift of the flat-band voltage (ΔVFB) of the nc-Si samples.
In the nitride memory, we know there are many deep energy-level of defect traps in this sample, and the carriers transport at low electric-field with hopping trapping named Poole-Frenkle emission. In the silicon oxide thin film, the carriers transport at high electrical–field names Fowler-Norhdiem effect tunneling, as is known to all.
Differ from the storage media containing two kinds of discrete charge storage centers: nitride traps in the case of SONOS and isolated Si nanocrystals in the flash memory, the Si NDs embedded in the (SiNx) thin film grown by plasma enhanced chemical vapor deposition has a larger window size of hysteresis in C-V curve. In this study, we observed the two different hysteresis phenomenon measured with the same repeated sweep voltage in the same device. We try to analyze the relationship between memory effect and the ratio of SiH4 and N2, and the different memory phenomenon from the traps and the silicon nano-dots. The Other thing is to investigate the carrier transport mechanism in the SiNx thin film.

[1.1] D. Kahng and S. M. Sze, “A floating gate and its application to memory devices,” Bell Syst. Tech. J., vol. 46, p.1288, 1967.
[1.2] H. A. R. Wegener, A. J. Lincoln, H. C. Pao, M. R. O’Connell, and R.E. Oleksiak, “The variable threshold transistor, a new electrically alterable, non-destructive read-only storage device,” IEEE IEDM Tech. Dig., Washington, D. C., 1967.
[1.3] D. Frohman-Bentchkowsky, “A fully decoded 2048-bit electrically programmable MOS-ROM,” IEEE ISSCC Dig. Tech. Pap., p. 80, 1971.
[1.4] D. Frohman-Bentchkowsky, “Memory behavior in a floating gate avalanche injection MOS (FAMOS) structure,” Appl. Phys. Lett., vol. 18, p332, 1971.
[1.5] D. Frohman-Bentchkowsky, “A fully decoded 2048-bit electrically programmable FAMOS read-only memory,” IEEE Trans. Elect. Dev., vol. ED-25, p 1277, 1978.
[1.6] D. Frohman-Bentchkowsky, “FAMOS-A new semiconductor charge storage device,” Sol. St. Electr., vol. 17, p 517, 1974.
[1.7] H. lizuka, T. Sato, F. Masuoka, K. Ohuchi, H. Hara, H. Tango, M. Ishikawa, and Y. Takeishi, "Stacked gate avalanche injection type MOS (SAMOS) memory," Proc. 4th Conf. Sol. St. Dev., Tokyo, 1972; J. Japan. Soc. Appl. Phys., vol. 42, p. 158, 1973.
[1.8] H. lizuka, F. Masuoka, T. Sato, and M. Ishikawa, "Electrically alterable avalanche injection type MOS read-only memory with stacked gate structure, " IEEE Trans. Elect. Dev., vol. ED-23, p. 379, 1976.
[1.9] W. Johnson, G. Perlegos, A. Renninger, G. Kuhn, and T. Ranganath, "A 16k bit electrically erasable non-volatile memory, in Tech. Dig. IEEE ISSCC, p. 152, 1980
[1.10] Kume, H. et al. (1987) A Flash-Erase EEPROM Cell with an Asymmetrical Source and Drain Structure, IEDM Proceedings, p. 560.
[1.11] Masuoka, F. et al (1984) A new flash EEPROM cell using triple polysilicon technology, IEDM Proceedings, p. 464.
[1.12] Samachisa, G. et al. (1987) A128k Flash EEPROM Using Double-Polysilicon Technology, IEEE Journal of Solid State Circuits, vol. SC-22, No. 5, October 1987, p. 676.
[1.13] F. Masuokaand K. Sakui, "Technology trend of Flash EEPROM," Ext. Abstract of SSDM, p.877-p.979, 1993
[1.14] H. Kume, M. Kato, T. Adachi, T. Tanaka, T. Sasaki, T. Okazaki, "A 1.28um2 contactless memory cell technology for a 3V- only 64M bit EEPROM," in IEDM Tech. Dig., p.991-p.993, 1992
[1.15] Y. S. Hisamune, K. Kanamori, T. Kubota, Y. Suzuki, M. Tsukiji, E. Hasegawa, et. al., "A high capacitive-coupling ratio (HiCR)cell for 3V-only 64 M bit and future Flash memories" in IEDM Tech. Dig., p. 19-p.22, 1993
[1.16] B. Guillaumot, Ph. Candelier and F. Martin, "A 13.5 nm Full LPCVD NO and ONO interpoly dielectric for 0.25mm nonvolatile memory process," in intl. NVM workshop, 1995
[1.17] T. Kobayashi, A. Katayama; H. Kume and K. Kimura, "NH3-annealed and wet-oxidized CVD Si02 single-layer interpoly dielectric for highly integrated Flash memories," in intl. NVM workshop, 1997
[1.18] S.Yamada, T.Suzuki, E.Obi, M.Oshikiri, K.Naruke and M.Wada, "A self-convergence erasing scheme for a simple stacked gate Flash EEPROM," in IEDM Tech. Dig., p.307-310, 1991
[1.19] D.P.Dhum, C.T.Swift, J.M.Higman, W.J.Taylor, K.T.Chang, K.M.Chang and J.R.Yeargain, "A novel band-to-band tunneling induced convergence mechanism for low current, high density Flash EEPROM applications," in IEDM Tech. Dig.,p.41-p.44, 1994
[1.20] C.-Y.Hu, D.L.Kencke, S.K.Banerjee, R.Richart, B. Bandyopadhyay, B.Moore, E.Ibok and S.Garg, "A convergence scheme for over-erased Flash EEPROM's using substrate-bias-cnhanced hot electron injection," IEEE Electron Device Lett., vol.EDL-16, no.l 1, p.500-p.502, 1995
[1.21] Ph.Candelier, F.Mondon, G.Buillaumot, G.Reimbold, H.Achard, F.Martin and J.Hartmann, "Hot carrier self-convergent programming method for multi-level Flash cell memory," in Proc. IEEE/IRPS, p.l04-p.l09, 1997
[1.22] C.-S.Yang, Y.-S.Wang, S.-J. Shen, C.-J.Lin, M. S.Liang, C.C-H.Hsu, "New Self-Convergent Programming Method for Multi-Level AND Flash Memory," submitted to IEEE Electron Device Letter.
[1.23] S. Tiwari, et al, “Volatile and Non-volatile Memories in Silicon with Nanocrystal Storage”, (IBM) IEDM, December 1995, pp521.
[1.24] S. Tiwari, et al, “Single charge and confinement effects in nano-crystal memories”, Appl. Phys. Lett, 69(9), August 1996.
[1.25] J. A. Wahl, et al, “Write, Erase and storage Times in Nanocrystal Memories and the Role Interface States, (IBM) IEDM, December, 1999, pp375.
[1.26] J. J. Welser, et al, “Room Temperature Operation of a Quantum-Dot Flash Memory”, IEEE Electron Device Letter, Vol. 18, NO. 6, June 1997 ,pp278.
[1.27] O. Winkler , et al, “Concept of floating-dot memory transistors on silicon-on-insulator substrate”, Microelectronic Engineering, 61-61 (2002), pp497.
[1.28] T. Ishii, et al, “Engineering Variation : Towards Practical Single-Electron (Few-Electron) Memory”, IEDM, December 2000, pp305.