簡易檢索 / 詳目顯示

回結果列表
研究生： 鄭佳文
Cheng, Chia-Wen
論文名稱： FinFET之閘極電阻對電路效能及設計流程的影響
FinFET Gate Resistance Impacts on Circuit Performance and Design Flow
指導教授： 張彌彰
Chang, Mi-Chang
口試委員: 馬席彬
Ma, Hsi-Pin
徐永珍
Hsu, Yung-Jane
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電子工程研究所
Institute of Electronics Engineering
論文出版年： 2020
畢業學年度： 108
語文別： 英文
論文頁數： 120
中文關鍵詞： 閘極電阻 、電路效能 、設計流程
外文關鍵詞： FinFET, Resistance, Performance
相關次數： 點閱：2  下載：0 
分享至:
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報

    • FinFET是20奈米以下半導體技術的主要選擇。由於其立體的結構，寄生效應相較於平面的電晶體更為顯著。在這篇論文中，我們探討寄生電阻、電容對反相器(inverter)和環形震盪器(ring oscillator)效能的敏感度。此外，我們驗證了經由查表方式來計算延遲時間與功率消耗的數位設計流程，即使將寄生電阻的影響納入考慮仍可使用。
    首先，為了提升3D FinFET模擬所需的準確度與效率，必須將網格的架構最佳化。然後，使用優化後的網格進行一系列的實驗，觀察寄生電阻電容對電路效能的影響。我們發現10kΩ的多晶矽閘極電阻對於有4個fin的反相器的平均延遲時間增加9.69%，而對於有6個fin的反相器的平均延遲時間的增加則是上升到10.58%。
    我們證明了即便將寄生電阻的影響納入考慮，Logical Effort仍然不失為一種估計延遲時間的好方法。此外，我們也驗證了一般常見的數位設計方法仍然適用，但表格需要根據不同的電阻值修改。

    FinFET is the main device option for sub-20nm technology nodes. Owing to the three-dimensional structure, parasitic effects are more significant than planer transistors. In this thesis, the sensitivity of parasitics on inverter and ring oscillator performance is studied. Moreover, taking the parasitic resistance into account, we verified that the design flow of inverter delay and power calculation based on table look-up approach can still be used.
    The mesh structure is optimized first to obtain the desired accuracy and efficiency of 3D FinFET simulations. Then, using this optimized mesh, a series of simulations are performed to observe the impacts of parasitic resistance and capacitance on circuit performance. It was found that the 10kΩ poly gate resistance makes 9.69% increase of INV average delay time with 4-fins, while the 10kΩ poly gate resistance makes 10.58% increase of INV average delay time with 6-fins.
    It is demonstrated that logical effort is still a good way to estimate the delay by taking the parasitic resistance into account. Moreover, we also verified that the conventional approach for digital design is still applicable, while the tables need to be modified with different resistance.

    摘要 i Abstract ii 致謝 iii List of Tables viii List of Figures x Chapter 1 Introduction 1 1.1 Background 1 1.2 Parasitic Resistance and Capacitance 2 1.3 Thesis Organization 3 Chapter 2 FinFET Structures 4 2.1 Introduction 4 2.2 TCAD Simulation Setup 5 2.3 Mesh Optimization 8 2.3.1 On both sides of the channel 9 2.3.2 Above the channel 17 2.3.3 Below the channel 24 2.3.4 Z direction of the channel 31 2.4 Comparing Bulk/SOI FinFET and GAA-FET 34 2.5 CMOS Inverter 37 2.6 Summary 41 Chapter 3 Impacts of Parasitic Resistance 42 3.1 Introduction 42 3.2 Re-meshing 43 3.3 Lumped Resistance Model Impacts on INV Performance 46 3.3.1 Input Delay 49 3.3.2 Input Slew 51 3.3.3 Overshoot and Undershoot 51 3.4 Distributed Resistance Model Impacts on INV Performance 53 3.4.1 Input Delay 56 3.4.2 Input Slew 59 3.4.3 Overshoot and Undershoot 60 3.5 Comparing Lumped and Distributed Resistance Model 62 3.6 Lumped Resistance Model Impacts on Ring Oscillator 63 3.7 Summary 67 Chapter 4 Impacts of Parasitic Capacitance 68 4.1 Introduction 68 4.2 Lumped RC Model Impacts on INV Performance 69 4.2.1 Input Delay 71 4.2.2 Input Slew 73 4.2.3 Overshoot and Undershoot 74 4.3 Distributed RC Model Impacts on INV Performance 76 4.3.1 Input Delay 79 4.3.2 Input Slew 82 4.3.3 Overshoot and Undershoot 84 4.4 Comparing Lumped and Distributed RC Model 85 4.5 Summary 86 Chapter 5 Parasitic Resistance Impacts on Digital Design 88 5.1 Introduction 88 5.2 Impacts of Poly Gate Resistance 89 5.3 Logical Effort 92 5.4 INV Chain Delay 96 5.5 Two-dimensional Table 99 5.6 Comparison between Table and Simulation Results 106 5.7 Impacts of Interconnect Resistance 109 5.8 Summary 113 Chapter 6 Conclusions and Future Work 114 6.1 Conclusions 114 6.2 Future Work 116 References 117

    [1] C. R. Manoj, Angada B. Sachid, Feng Yuan, Chang-Yun Chang, and V. Ramgopal Rao, “Impact of Fringe Capacitance on the Performance of Nanoscale FinFETs,” IEEE Electron Device Letters, pp. 83-85, vol. 31, no.1, Jan. 2010.
    [2] Kyeungkeun Choe, TaeYoon An, and SoYoung Kim, “Accurate Fringe Capacitance Model Considering RSD and Metal Contact for Realistic FinFETs and Circuit Performance Simulation,” International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Sept. 2014.
    [3] Kenichi Miyaguchi, Bertrand Parvais, Lars-Åke Ragnarsson, Piet Wambacq, Praveen Raghavan, Abdelkarim Mercha, Anda Mocuta, Diederik Verkest, and Aaron Thean, “Modeling FinFET Metal Gate Stack Resistance for 14nm Node and Beyond,” International Conference on IC Design & Technology (ICICDT), June 2015.
    [4] Edgar Solis Avila, Julio C. Tinoco, Andrea G. Martinez-Lopez, Mario Alfredo Reyes-Barranca, Antonio Cerdeira, and Jean-Pierre Raskin, “Parasitic Gate Resistance Impact on Triple-Gate FinFET CMOS Inverter,” IEEE Transactions on Electron Devices, pp. 2635-2642, vol. 63, no.7, July 2016.
    [5] Divya Prasad, and Azad Naeemi, “Interconnect design for evolutionary, and revolutionary transistor technologies,” IEEE International Interconnect Technology Conference (IITC), May 2017.
    [6] C. Auth, A. Aliyarukunju, M. Asoro, D. Bergstrom, V. Bhagwat, J. Birdsall, N. Bisnik, M. Buehler, V. Chikarmane, G. Ding, Q. Fu, H. Gomez, W. Han, D. Hanken, M. Haran, M. Hattendorf, R. Heussner, H. Hiramatsu, B. Ho, S. Jaloviar, I. Jin, S. Joshi, S. Kirby, S. Kosaraju, H. Kothari, G. Leatherman, K. Lee, J. Leib, A. Madhavan, and K. Marla, “A 10nm high performance and low-power CMOS technology featuring 3rd generation FinFET transistors, Self-Aligned Quad Patterning, contact over active gate and cobalt local interconnects,” IEEE International Electron Devices Meeting (IEDM), Dec. 2017.
    [7] S. Barraud, V. Lapras, B. Previtali, M.P. Samson, J. Lacord, S. Martinie, M.-A. Jaud, S. Athanasiou, F. Triozon, O. Rozeau, J.M. Hartmann, C. Vizioz, C. Comboroure, F. Andrieu, J.C. Barbé, M. Vinet, and T. Ernst, “Performance and Design Considerations for Gate-All-Around Stacked-NanoWires FETs,” IEEE International Electron Devices Meeting (IEDM), Dec. 2017.
    [8] Y.M. Lee, M.H. Na, A. Chu, A. Young, T. Hook, L. Liebmann, E.J. Nowak, S.H. Baek, R. Sengupta, H. Trombley, and X. Miao, “Accurate Performance Evaluation for the Horizontal Nanosheet Standard-Cell Design Space Beyond 7nm Technology,” IEEE International Electron Devices Meeting (IEDM), Dec. 2017.
    [9] Angada B. Sachid, Min-Cheng Chen, and Chenming Hu, “Bulk FinFET With Low-κ Spacers for Continued Scaling,” IEEE Transactions on Electron Devices, pp. 1861-1864, vol. 64, no.4, April 2017.
    [10] Xi Zhang, Daniel Connelly, Hideki Takeuchi, Marek Hytha, Robert J. Mears, and Tsu-Jae King Liu, “Comparison of SOI Versus Bulk FinFET Technologies for 6T-SRAM Voltage Scaling at the 7-/8-nm Node,” IEEE Transactions on Electron Devices, pp. 329-332, vol. 64, no.1, Jan. 2017.
    [11] Sandeep Miryala, Baljit Kaur, Bulusu Anand, and Sanjeev Manhas, “Efficient Nanoscale VLSI Standard Cell Library Characterization Using a Novel Delay Model,” 12th International Symposium on Quality Electronic Design, March 2011.
    [12] Wen Wu, and Mansun Chan, “Gate resistance modeling of multifin MOS devices,” IEEE Electron Device Letters, pp. 68-70, vol. 27, no.1, Jan. 2006.
    [13] Hisakazu Edamatsu1, Katsumi Homma, Masaru Kakimoto, Yutaka Koike, and Kinya Tabuchi, “Pre-layout delay calculation specification for CMOS ASIC libraries,” Proceedings of 1998 Asia and South Pacific Design Automation Conference, Feb. 1998.
    [14] Chandan Kumar Sarkar (2013). Technology Computer Aided Design: Simulation for VLSI MOSFET. Boca Raton, London, New York: CRC Press.
    [15] Ivan Sutherland, Bob Sproull, and David Harris (1999). Logical Effort: Designing Fast CMOS Circuits. San Francisco, Calif.: Morgan Kaufmann Publishers.
    [16] SILVACO, DevEdit User’s Manual, Jan. 2014.
    [17] SILVACO, Atlas User’s Manual: DEVICE SIMULATION SOFTWARE, Aug. 2016.

    QR CODE