在現今的電子產品中，大多數電子設備仍然依賴石英振盪器產生時脈訊號，主要是因為石英振盪器提供了目前最高的頻率穩定性，然而，石英晶體作為振盪器的基本元件，有大面積、高成本、高消耗功率，以及無法與CMOS製成做整合等的缺點，因此過去幾十年來各界學者都試圖尋找能替代石英振盪器的方案。
近年來被提出取代石英振盪的方法有MEMS振盪器、FBAR振盪器以及CMOS振盪器。但是，MEMS與FBAR的製程技術困難，無法與CMOS電路整合；而CMOS振盪器因半導體特性易受環境影響，導致其振盪頻率會因環境溫度與供應電壓的變動而改變。因此至今石英振盪器還無法完全被取代。
CMOS電路在設計上可以透過回授與補償的機制提高穩定度，加上設計適當的電路架構減少雜訊，其中RC弛張振盪器作為一個參考頻率源，面積相較於LC振盪器更小，並且頻率穩定度比環形振盪器更高，因此被廣泛使用。
本次研究提出一個由TSMC 90nm 1P9M 標準製程下製作的穩定且低抖動的時脈產生器。透過平均電壓值回授、電組的串並聯或並串聯以及對整體電路做溫度補償這三個概念，保持輸出頻率穩定。此外，透過單一充放電路徑並在輸出加上一個除頻器，使輸出訊號為接近50.0% duty cycle的方波。最後，結合斜率提升的技術，在低功率消耗的條件下減少抖動，實現一個穩定且低抖動的參考頻率源。

In today's electronic products, most electronic devices still rely on quartz oscillators to generate clock signals, primarily because quartz oscillators offer the highest frequency stability available today. However, quartz crystals, as the fundamental component of oscillators, have disadvantages such as large size, high cost, high power consumption, and the inability to integrate with CMOS processes. As a result, researchers have been exploring alternatives to quartz oscillators over the past few decades.
In recent years, alternatives to quartz oscillators, such as MEMS oscillators, FBAR oscillators, and CMOS oscillators, have been proposed. However, MEMS and FBAR technologies face manufacturing challenges and cannot be integrated with CMOS circuits. Additionally, CMOS oscillators are prone to environmental influences due to the characteristics of semiconductors, causing their oscillation frequency to fluctuate with changes in operating temperature and supply voltage. Therefore, quartz oscillators have not yet been fully replaced.
In CMOS circuit design, stability can be enhanced through feedback and compensation mechanisms, along with the design of appropriate circuit architectures to reduce noise. Among these, the RC relaxation oscillator, used as a reference frequency source, occupies a smaller area compared to an LC oscillator and offers better frequency stability than a ring oscillator, making it widely adopted.
This study proposes a stable and low-jitter clock generator fabricated using the TSMC 90nm 1P9M standard process. The output frequency is stabilized through three concepts: Voltage Average Feedback, series-parallel or parallel-series component configurations, and temperature compensation for the entire circuit.. Additionally, employing a single charge-discharge path and adding a frequency divider at the output results in a square wave with a near 50.0% duty cycle. Finally, the integration of slope enhancement techniques reduces jitter under low power consumption, achieving a stable and low-jitter reference frequency source.

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