毫米波雙頻並行之收發機前端電路設計｜國立清華大學博碩士論文庫

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研究生：	潘厚儒 Pan, Hou-Ru
論文名稱：	毫米波雙頻並行之收發機前端電路設計 Design of Millimeter-Wave Concurrent Dual-Band Transceiver Front-End Circuits
指導教授：	劉怡君 Liu, Yi-Chun
口試委員:	徐碩鴻 Hsu, Shou-Hung 林佑昇 Lin, Yo-Sheng
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2018
畢業學年度：	106
語文別：	英文
論文頁數：	127
中文關鍵詞：	雙頻並行、功率放大器、低雜訊放大器、壓控震盪器、毫米波、90奈米CMOS 、匹配網路
外文關鍵詞：	Concurrent dual-band, Power amplifier, Low noise amplifier, Voltage-controlled oscillator, Millimeter-wave, 90-nm CMOS, Matching network
相關次數：	點閱：3 下載：0
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隨著半導體產業的發展，電晶體也越做越小，帶來的是晶片面積縮小與耗能降低，而需要小尺寸晶片的產品如行動裝置與車用電子也蓬勃發展中，加上無線通訊的應用，使得電晶體的操作頻率越趨高頻，為了得到更寬的頻寬一方面能加速資料的傳輸，另一方面可以增加使用者數目。現今大部分的無線收發機電路仍以使用矽製程為主，因大多數的產品以低成本及低功耗為主要考量。
在未來手機會使用到的頻段以第五代通訊系統(5th Generation)與電機電子工程學會(IEEE)所制定的無線區域網路(wireless local area networks, WLAN)標準為主要應用，前者的頻率各國仍在研討中，目前可能會用到的頻率有28、38 GHz，而下一代的無線區域網路標準為802.11.ad，所使用的頻率是60 GHz，而38、60 GHz為此論文所研究的頻率。
本論文探討了雙頻並行的收發機前端子電路設計，並利用90奈米互補式金屬氧化物半導體(Complementary Metal-Oxide-Semiconductor, CMOS)製程實現。第一個設計為功率放大器，可同時操作於Ka與V頻帶，所能達到的飽和功率輸出分別為7.2與7.3 dBm，最大的功率附加效率分別為4.1與4.6%，而第二個設計為低雜訊放大器，同樣可同時操作於前述兩個頻帶，雜訊指數分別為5.6與6.2 dB，並有13.4和11 dB的線性增益，最後一個設計為壓控振盪器，一樣可同時操作該兩頻帶，該設計在1 MHz的相位雜訊為-99.8和-93.1 dBc/Hz，並有8%和9.5%的頻率調整範圍。

As the fast development of semiconductor industry, the transistor size is thinking that leads to smaller chip size and lower energy consumption. The mobile devices and automotive electronics that demand small size are very popular. The applications of wireless communications make transistor operate in higher frequency to get the wider bandwidth hence the data transfer can be faster and the number of users can be increased. Most of the wireless transceiver circuits use silicon process nowadays for its low cost and low power dissipation.
In the future, 5th generation communication systems and a new protocol of WLAN developed by IEEE will be the main application bands for mobile phones. The operation band in the former is still under discussion in each country where 28 GHz and 38 GHz are the candidate frequency bands. Next generation of WLAN is 802.11.ad that uses 60 GHz as operation frequency band. Thus, the frequencies of interest in this thesis are 38 GHz and 60 GHz.
The thesis discusses the design of concurrent dual-band transceiver front-end circuits implemented by TSMC 90-nm CMOS process. The first design is a power amplifier operating at Ka-band and V-band concurrently. Its saturation output power is 7.2 dBm and 7.3 dBm at two bands, respectively. The maximum power-added-efficiency (PAE) is 4.1% and 4.6% at two bands, respectively. The second design is a low noise amplifier operating at dual bands simultaneously with 5.6 dB and 6.2 dB noise figure where its linear gain is 13.4 dB and 11.1 dB, respectively. The last design is a voltage-controlled oscillator. It generates two non-harmonic output frequencies in the same power spectrum. In this design, the phase noise is -99.8 dBc/Hz and -93.1 dBc/Hz at 1 MHz with 8% and 9.5% tuning range in two bands.

摘要    i
ABSTRACT    ii
Contents    i
List of Figures    v
List of Tables    xi
Chapter 1    Introduction    1
1.    Introduction to Millimeter-wave    1
2.    Introduction to Multi-Band Systems    1
3.    Compare Dual-Band and Concurrent Dual-Band    2
4.    Structures of Concurrent Dual-Band in Amplifiers    3
4.1    Broadband Amplifier with a Notch Filter    3
4.2    Amplifier with Dual-band Matching    4
5.    Structures of Concurrent Dual-Band in Oscillators    4
6.    The Research Topic and Motivation in This Thesis    5
Chapter 2    Devices in TSMC 90-nm CMOS Process    6
1.    Passive Devices    6
1.1    Inductors    6
1.2    Capacitors    10
1.2.1    MOM Capacitors    10
1.2.2    MIM Capacitors    12
2.    Active Devices    13
Chapter 3    A 38/60 GHz Concurrent Dual-Band Power Amplifier    17
1.    Introduction of Power Amplifiers    17
2.    Specifications of Power Amplifiers    19
2.1    Specifications of Small Signal Operation    19
2.1.1    S-Parameters    19
2.1.2    Stability    21
2.2    Specifications of Large Signal Operation    23
2.2.1    Output Power    23
2.2.2    Efficiency    24
2.2.3    Linearity    25
3.    Classification of Power Amplifiers    27
4.    Load Line Theory    31
5.    Dual-Band Matching Network    33
5.1    Network A    33
5.2    Network B    36
5.3    Network C    39
6.    The Proposed Power Amplifier    41
6.1    Paper Survey    41
6.2    Circuit Design    42
6.2.1    Sizing    42
6.2.2    Matching Network    44
6.2.3    Post-Layout Simulation    51
6.3    Simulation and Measurement Results    52
6.4    Conclusions    64
Chapter 4    A 38/60 GHz Concurrent Dual-Band Low Noise Amplifier    69
1.    Introduction of Low Noise Amplifiers    69
2.    Specifications of Low Noise Amplifiers    69
2.1    Noise Figure    69
2.2    Stability    74
3.    The Proposed Low Noise Amplifier    75
3.1    Paper Survey    75
3.2    Circuit Design    75
3.2.1    Sizing    76
3.2.2    Matching Network    80
3.2.3    Post-Layout Simulation    83
3.3    Simulation and Measurement Results    84
3.4    Conclusions    95
Chapter 5    A 38/60 GHz Dual-Band Voltage-Controlled Oscillator    97
1.    Introduction of Voltage-Controlled Oscillators    97
2.    Specifications of Voltage-Controlled Oscillators    97
2.1    Phase Noise    97
2.2    Tuning Range    103
3.    The Proposed Voltage-Controlled Oscillator    105
3.1    Paper Survey    105
3.2    Circuit Design    106
3.2.1    Structures Selection    106
3.2.2    Sizing    107
3.2.3    Coupled Inductors    109
3.2.4    Post-Layout Simulation    111
3.3    Simulation and Measurement Results    112
3.4    Conclusions    119
Chapter 6    Conclusions and Future Works    121
Reference    124

                                

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