Standalone的監視系統相較於一般的PC-based的監視系統，其優點在於成本低、堅固、維修方便、體積小。而多Channel的監視系統更可以有效利用硬體，且合乎各種安全性監視的應用，故本論文的目的在於設計一個即時的4-Channel standalone DVR監視系統架構，其影像品質高達30 field/sec/channel。除此之外，系統還能提供額外智慧型監視功能的擴充性，如智慧搜尋、樣型識別等。為了達成此目標，我們最初的構想是在4-channel DVR系統架構裡使用一顆DSP晶片(TI TMS320C6711)作為核心，以提供系統功能擴充的彈性。兩顆以小波轉換為基礎的影像壓縮解壓縮晶片(ADV612)，提供高品質的影像壓縮效能。另外，以三顆FPGA (ALTERA EP1C3T144C8)來做控制邏輯的介面及影像訊號的多工器/解多工器。接著，我們設計數位影像多工器(MUX)的電路，將4-channel數位影像輸入做multiplex合併，再送給ADV612做壓縮。影像播放時，所設計的解多工器(DEMUX)會將經過ADV612解壓送出的合併資料做de-multiplexer拆解，產生出四組影像資料。由於4-channel影像訊號輸入並非同步，因此MUX/DEMUX的設計必須要有額外的video field buffer。考慮到容量、價格及速度，選擇SDRAM來當作buffer最合適。因此，在FPGA裡還設計了SDRAM controller電路。在此，完成一個4-channel DVR system測試電路板的設計與實作，並成功的驗證MUX/DEMUX的效果及功能。由於選用FPGA做電路設計，未來此系統可輕易地增加額外的附加功能，如直接讀取出raw image來做智慧型處理，像是樣型識別、on-screen display (OSD)。也可以在NTSC blanking訊號存入語音資料和一些重要的資訊。另外還可以做畫面暫停、縮放、四分割或子母畫面輸出等功能。

In contrast with PC-based Digital Video Recorder (DVR) system in surveillance applications, the standalone DVR has several advantages such as lower cost, more rugged, easier maintenance, and smaller size. Moreover, the multi-channel design can further increase the utilization efficiency of the DVR hardware and meet the various demands of increasing surveillance applications. In this study, our goal is to design a standalone 4-channel DVR system which exhibits the real-time, high video quality (up to 30 fields/sec/channel high-quality NTSC signal) capabilities. In addition, the system should allow for easy extension to accommodate intelligent surveillance functions, such as intelligent search, pattern recognition, etc. To meet these goals, we first propose the system architecture of a 4-channel DVR which uses a DSP chip (TI’s TMS320C6711) as its central unit providing the flexibility of adding more functionalities to the DVR, two wavelet-based video chips (ADV612) as the compression/decompression engine to achieve high image quality and compression efficiency, and three FPGA chips (ALTERA EP1C3T144C8) for interface logic and video signal multiplexer/de-multiplexer. Then we designed a digital video multiplexer (MUX) circuit to multiplex the incoming 4-channel input digital video signals together to be compressed by the ADV612 compression chip. During playback, a video de-multiplexer (DEMUX) circuit is also designed to generate 4 channel full video signals from the decompressed output video signal of the ADV612. Considering the asynchronous characteristics of the incoming 4 channel video signals, at least a video field buffer is needed in the MUX/DEMUX design, which is best implemented by SDRAM due to its capacity/cost/speed requirements. Therefore, an SDRAM controller circuit is also designed on the same FPGA. A prototype 4-ch DVR system board has been designed and implemented which successfully illustrated the validity and functionality of our MUX, DEMUX design. Furthermore, the use of FPGA in our design could easily allow for many extra functions to be implemented into the system, such as raw image extraction for intelligent DVR like pattern recognition, on-screen display (OSD), information or audio insertion into NTSC blanking, as well as freeze, zoom, quadrant and PIP functions, etc.

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