目前快閃記憶體元件之原理乃是利用電子儲存於懸浮閘極中，藉由起始電壓的偏移來判別記憶與否。傳統懸浮閘極記憶元件是利用導電的複晶矽作為懸浮閘極的材料，當複晶矽形成之懸浮閘極若產生局部漏電將導致全面性的漏電問題。有鑑於此，利用已被廣泛研究的奈米晶結構來取代傳統的懸浮閘極，其中奈米晶粒彼此間擁有良好的絕緣等特性，故在漏電問題上，克服了傳統懸浮閘極全面漏電的危險。
在實驗的部份，利用熱成長、磁控濺鍍與原子層化學氣相沉積法(ALCVD)成長穿隧氧化層-PtOx-閘極氧化層結構，再加以熱處理使PtOx以自組裝的方式還原成Pt奈米晶陣列，並製作成MOS結構，而對此MOS結構作有關C-V、I-V與retention的量測分析，得以確認奈米晶捕獲電荷的能力。
本論文當中將探討閘極介電層材料結構的影響。此MOS電容可視為控制層電容Cco與穿隧層電容Cto串聯，由於奈米晶之充放電取決於穿隧層所受電壓，而此電壓Vto與施加於閘極的電壓Vg的關係為Vto=Vg．Cco/(Cco+Cto)，因此在同樣的介電層厚度下，採用較高介電係數的控制層材料，對特定的Vto，所需的Vg較低，故有利於操作電壓的降低，同時也將比較不同閘極材料下，對於漏電流的影響，及對於侷限電子的持久性(retention)的比較。

1. TRI產業專業報告-11 席捲記憶體市場之未來新霸主-快閃記憶體 拓墣產業研究所 2004 六月
2. 電子與材料雜誌 第24期 奈米電子元件：張鼎張、顏碩廷、劉柏村；單電子電晶體：胡淑芬
3. S. Tiwari, F. Rana, H. Hanafi, A. Hartstein, E. F. Crabbe, and K. Chan, “A silicon nanocrystals based memory”, Appl. Phys. Lett. 68, 1377 (1996).
4. L. Guo, E. Leobandung, and S. Y. Chou, “A silicon single-electron transistor memory operating at room temperature”, Science 275, 649 (1997).
5. Y. Shi, K. Saito, H. Ishikuro, and T. Hiramoto, “Effects of traps on charge storage characteristics in metal-oxide-semiconductor memory structures based on silicon nanocrystals”, J. Appl. Phys. 84, 2358 (1998).
6. I. Kim, S. Han, K. Han, J. Lee, and H. Shin, “Room temperature single electron effects in a Si nanocrystal memory”, IEEE Electron Device Letters 20(12), 630 (1999).
7. M. Saitoh, E. Nagata, and T. Hiramoto, “Large memory window and long charge-retention time in ultranarrow channel silicon floating-dot memory”, Appl. Phys. Lett. 82, 1787 (2003).

8. B. Garrido, S. Cheylan, O. Gonzalez-Varona, A. Perez-Rodriguez, and J. R. Morante, ”The effect of additional oxidation on the memory characteristics of metal-oxide –semiconductor capacitors with Si nanocrystals”, Appl. Phys. Lett. 82, 4818 (2003).
9. Y.-C. King, T.-J. King, and C. Hu, “Charge-trap memory device fabricated by oxidation of Si1-xGex”, IEEE Trans. Electron Devices 48, 696 (2001).
10. Y.-C. King, T.-J. King, and C. Hu, “MOS memory using germanium nanocrystals formed by thermal oxidation of Si1-xGex”, IEDM Tech. Dig., 98 (1998).
11. V. Ho, L. W. Teo, W. K. Choi, W. K. Chim, and M. S. Tay, “Effect of germanium concentration and tunnel oxide thickness on nanocrystal formation and charge storage/retention characteristics of a trilayer memory structure”, Appl. Phys. Lett. 83, 3558 (2003).
12. M. Kanoun and A. Souifi, “Electrical study of Ge-nanocrystal-based metal oxide-semiconductor structure for p-type nonvolatile memory applications”, Appl. Phys. Lett. 84, 5079 (2004).
13. Ying Qian Wang, Jing Hao Chen, Won Jong Yoo, Yee-Chia Yeo, Sun Jung Kim, Rohit Gupta, and Zerlinda Y. L. Tan, ”Formation of Ge nanocrystals in HfAlO high-k dielectric and application in memory device”, Appl. Phys. Lett. 84, 5047 (2004).
14. W. L. Liu, P. F. Lee, J. Y. Dai, J. Wang, H. L. W. Chan, and C. L. Choy, ”Self-organized Ge nanocrystals embedded in HfAlO fabricated by pulsed-laser deposition and application to floating gate memory”, Appl. Phys. Lett. 86, 013110 (2005).
15. X. B. Lu, P. F. Lee, and J. Y. Dai, “Synthesis and memory effect study of Ge nanocrystals embedded in LaAlO3 high-k dielectrics”, Appl. Phys. Lett. 86, 203111 (2005).
16. Z. Liu, C Lee, V. Narayanan, G. Pei, and E. C. Kan, “Metal nanocrystal memories—partⅠ：device design and fabrication”, IEEE Trans. Electron Devices 49, 1606 (2002).
17. Z. Liu, C Lee, V. Narayanan, G. Pei, and E. C. Kan, “Metal nanocrystal memories—partⅡ：electrical and characteristics”, IEEE Trans. Electron Devices 49, 1614 (2002).
18. Jiun-Yi Tseng, Cheng-Wei Cheng, Sheng-Yu Wang, and Tai-Bor Wu, “Memory characteristics of Pt nanocrystals self-assembled from reduction of an embedded PtOx ultrathin film in metal-oxide-semiconductor structures”, Appl. Phys. Lett. 85, 2595 (2004).
19. Zerlinda Tan, S. K. Samanta, Won Jong Yoo, and Sungjoo Lee, ”Self-assembly of Ni nanocrystals on HfO2 and N-assisted Ni confinement for nonvolatile memory application”, Appl. Phys. Lett. 86, 013107 (2005).
20. Jong Jin Lee, Yoshinao Harada, Jung Woo Pyun and Dim-Lee Kwong, ”Nickel nanocrystal formation on HfO2 dielectric for nonvolatile memory device applications”, Appl. Phys. Lett. 86, 103505 (2005).
21. H. I. Hanafi, S. Tiwari, and I. Khan, “Fast and long retention-time nano-crystal memory”, IEEE Trans. Electron Devices 43, 1553 (1996).
22. S. Tiwari, F. Rana, K. Chan, L. Shi, and H. Hanafi, “Single charge and confinement effects in nano-crystal memories”, Appl. Phys. Lett. 69, 1232 (1996).
23. N. Takahashi, H. Ishikuro, and T. Hiramoto, “Control of Coulomb blockade oscillations in silicon single electron transistors using silicon nanocrystal floating gates”, Appl. Phys. Lett. 76, 209 (2000).
24. E. Kapetanakis, P. Normand, and D. Tsoukalas, “Room temperature single-electron charging phenomena in large-area nanocrystal memory obtained by low-energy ion beam synthesis”, Appl. Phys. Lett. 80, 2794 (2002).
25. Jong Jin Lee, Xuguang Wang, Weiping Bai, Nan Lu, and Dim-Lee Kwong, “Theoretical and Experimental Investigation of Si Nanocrystal Memory Device With HfO2 High-k Tunneling Dielectric”, IEEE Trans. Electron Devices 50, 2067 (2003).
26. Sangmoo Choi, Myungjun Cho, and Hyunsang Hwang, “Improved metal-oxide-nitride-oxide-silicon-type flash device with high-k dielectrics for blocking layer”, J. Appl. Phys. 94, 5408 (2003).
27. T. C. Chang, S. T. Yan, C. H. Hsu, M. T. Tang, and J. F. Lee, “A distributed charge storage with GeO2 nanodots”, Appl. Phys. Lett. 84, 2581 (2004).
28. Rohit Gupta, Won Jong Yoo, Yingqian Wang, Zerlinda Tan, Ganesh Samudra, Sungjoo Lee, Daniel S. H. Chan, and Kian Ping Loh, “Formation of SiGe nanocrystals in HfO2 using in situ chemical vapor deposition for memory applications”, Appl. Phys. Lett. 84, 4331 (2004).
29. T. Ohzone, T. Matsuda, and T. Hori, “Erase/write cycle test of n-MOSFET’s with Si-implanted gate-SiO2”, IEEE Trans. Electron Devices 43, 1374 (1996).
30. C. Lee, Z. Liu and E. C. Kan, “Investigation on process dependence of self-assembled metal nanocrystals”, Mater. Res. Soc. Symp. Proc. 737, F8. 18. 1 (2003).
31. W. K. Choi and W. K. Chim, “Observation of memory effect in germanium nanocrystals embedded in an amorphous silicon oxide matrix of a metal-insulator-semiconductor structure”, Appl. Phys. Lett. 80, 2014 (2002).
32. L. W. Teo, W. K. Choi, W. K. Chim, V. Ho, C. M. Moey, M. S. Tay, C. L. Heng, Y. Lei, D. A. Antoniadis, and E. A. Fitzgerald, “Size control and charge storage mechanism of germanium nanocrystals in a metal-insulator-semiconductor structure”, Appl. Phys. Lett. 81, 3639 (2002).
33. V. Ho, L. W. Teo, W. K. Choi, W. K. Chim, and M. S. Tay, “Effect of germanium concentration and tunnel oxide thickness on nanocrystal formation and charge storage/retention characteristics of a trilayer memory structure”, Appl. Phys. Lett. 83, 3558 (2003).
34. C. Lee, A. Gorur-Seetharam and E. C. Kan, “Operational and reliability comparison of discrete-storage nonvolatile memories: advantages of single-and double-layer metal nanocrystals”, IEDM Tech. Dig., 557 (2003).
35. H. Ishikuro and T. Hiramoto, “Influence of quantum confinement effects on single electron and single hole transistors”, IEDM Tech. Dig., 119 (1998).
36. T. Hiramoto, “To fill the gap between Si-ULSI and nanodevices”, International Journal of High Speed Electronics and Systems 10 (1), 197 (2000).
37. S. Huang, S. Banerjee, R. T. Tung, and S. Oda, “Quantum confinement energy in nanocrystalline silicon dots from high-frequency conductance measurement”, J. Appl. Phys. 94, 7261 (2003).
38. V. Ho, M. S. Tay, C. H. Moey, L. W. Teo, W. K. Choi, W. K. Chim, C. L. Heng, and Y. Lei, “Electrical characterization of a trilayer germanium nanocrystal memory device”, Microelectronic Engineering 66, 33 (2003).
39. 半導體元件(solid state electronic devices), Ben G. Streetman. Sanjay Banerjee 吳孟奇,洪勝富,連振炘,龔正 譯
40. P. Pavan, R. Bez, P. Olivo, and E. Zanoni, “Flash memory cells-an overview”, in proceedings of the IEEE, number 8, p. 1248 (1997).
41. A. K. Sharma, “Semiconductor memories”, IEEE press, New Jersey, 1997.
42. S. Tiwari, F. Rana, H. Hanafi, A. Hartstein, E. F. Crabbe, and K. Chan, “A silicon nanocrystals based memory”, Appl. Phys. Lett. 68, 1377 (1996).
43. B. Prince, “Emerging Memories–Technologies and Trends” by Kluwer Academic Publishers, p. 133 (2002).
44. T. Ohzone, T. Matsuda, and T. Hori, “Erase/write cycle test of n-MOSFET’s with Si-implanted gate-SiO2”, IEEE Trans. Electron Devices 43, 1374 (1996).
45. K. W. Guarini, C. T. Black, Y. Zhang, I. V. Babich, E. M. Sikorski, and L. M. Gignac, “Low voltage, scalable nanocrystal flash memory fabricated by templated self assembly”, IEDM Tech. Dig., 541 (2003).
46. S. J. Baik, S. Choi, U-In Chung, and J. T. Moon, “High speed and nonvolatile Si nanocrystal memory for scaled flash technology using highly field-sensitive tunnel barrier”, IEDM Tech. Dig., 545 (2003).
47. R. Muralidhar, R. F. Steimle, M. Sadd, R. Rao, C. T. Swift, E. J. Prinz, J. Yater, L. Grieve, K. Harber, and B. Hradsky, “A 6 V embedded 90 nm silicon nanocrystal nonvolatile memory”, IEDM Tech. Dig., 601 (2003).
48. G. Puzzilli, D. Caputo, and F. Irrera, “Fast and reliable tunnel programming of nanocrystal nonvolatile memories”, IEEE Trans. Electron Devices 51, 1205 (2004).
49. J. K. Kim. H. J. Cheong, Y. Kim, J. Y. Yi, H. J. Bark, S. H. Bang, and J. H. Cho, “Rapid-thermal-annealing effect on lateral charge loss in metal-oxide-semiconductor capacitors with Ge nanocrystals”, Appl. Phys. Lett. 82, 2527 (2003).
50. S. Tiwari, F. Rana, K. Chan, L. Shi, and H. Hanafi, “Single charge and confinement effects in nano-crystal memories”, Appl. Phys. Lett. 69, 1232 (1996).
51. H. I. Hanafi, S. Tiwari, and I. Khan, “Fast and long retention-time nano-crystal memory”, IEEE Trans. Electron Devices 43, 1553 (1996).
52. Y. Shi, K. Saito, H. Ishikuro, and T. Hiramoto, “Effects of traps on charge storage characteristics in metal-oxide-semiconductor memory structures based on silicon nanocrystals”, J. Appl. Phys. 84, 2358 (1998).
53. T. Hiramoto, “To fill the gap between Si-ULSI and nanodevices”, International Journal of High Speed Electronics and Systems 10 (1), 197 (2000).

54. N. Takahashi, H. Ishikuro, and T. Hiramoto, “Control of Coulomb blockade oscillations in silicon single electron transistors using silicon nanocrystal floating gates”, Appl. Phys. Lett. 76, 209 (2000).
55. M. Saitoh, E. Nagata, and T. Hiramoto, “Large memory window and long charge-retention time in ultranarrow channel silicon floating-dot memory”, Appl. Phys. Lett. 82, 1787 (2003).
56. E. Kapetanakis, P. Normand, and D. Tsoukalas, “Room temperature single-electron charging phenomena in large-area nanocrystal memory obtained by low-energy ion beam synthesis”, Appl. Phys. Lett. 80, 2794 (2002).
57. Z. Liu, C Lee, V. Narayanan, G. Pei, and E. C. Kan, “Metal nanocrystal memories—partⅠ：device design and fabrication”, IEEE Trans. Electron Devices 49, 1606 (2002).
58. Z. Liu, C Lee, V. Narayanan, G. Pei, and E. C. Kan, “Metal nanocrystal memories—partⅡ：electrical and characteristics”, IEEE Trans. Electron Devices 49, 1614 (2002).
59. C. Lee, A. Gorur-Seetharam and E. C. Kan, “Operational and reliability comparison of discrete-storage nonvolatile memories: advantages of single-and double-layer metal nanocrystals”, IEDM Tech. Dig., 557 (2003).
60. C. Lee, Z. Liu and E. C. Kan, “Investigation on process dependence of self-assembled metal nanocrystals”, Mater. Res. Soc. Symp. Proc. 737, F8. 18. 1 (2003).
61. W. K. Choi and W. K. Chim, “Observation of memory effect in germanium nanocrystals embedded in an amorphous silicon oxide matrix of a metal-insulator-semiconductor structure”, Appl. Phys. Lett. 80, 2014 (2002).
62. L. W. Teo, W. K. Choi, W. K. Chim, V. Ho, C. M. Moey, M. S. Tay, C. L. Heng, Y. Lei, D. A. Antoniadis, and E. A. Fitzgerald, “Size control and charge storage mechanism of germanium nanocrystals in a metal-insulator-semiconductor structure”, Appl. Phys. Lett. 81, 3639 (2002).
63. V. Ho, L. W. Teo, W. K. Choi, W. K. Chim, and M. S. Tay, “Effect of germanium concentration and tunnel oxide thickness on nanocrystal formation and charge storage/retention characteristics of a trilayer memory structure”, Appl. Phys. Lett. 83, 3558 (2003).
64. V. Ho, M. S. Tay, C. H. Moey, L. W. Teo, W. K. Choi, W. K. Chim, C. L. Heng, and Y. Lei, “Electrical characterization of a trilayer germanium nanocrystal memory device”, Microelectronic Engineering 66, 33 (2003).
65. H. Ishikuro and T. Hiramoto, “Influence of quantum confinement effects on single electron and single hole transistors”, IEDM Tech. Dig., 119 (1998).
66. P. Pavan, R. Bez, P. Olivo, and E. Zanoni, “Flash memory cells-an overview”, in proceedings of the IEEE, number 8, p. 1248 (1997).
67. R. Ohba, “Nonvolatile Si quantum memory with self-aligned doubly-stacked dots”, IEDM Tech. Dig., 313 (2000).
68. I. Kim, “Room temperature single electron effects in Si quantum dot memory with oxide-nitride tunneling dielectrics”, IEDM Tech. Dig., 111 (1998).
69. 半導體元件(solid state electronic devices), Ben G. Streetman. Sanjay Banerjee 吳孟奇,洪勝富,連振炘,龔正 譯
70. 白金奈米晶粒於金屬-氧化物-半導體結構中對非揮發性懸浮閘極記憶體應用之研究,清華大學博士論文,曾駿逸博士
71. C. Lee, A. Gorur-seetharam and E. C. Kan, Tech. Dig. Int. Electron Devices Meet, 557 (2003).
72. Y. Shi, K. Saito, H. Ishikuro, and T. Hiramoto, J. Appl. Phys. 84, 2358 (1998).
73. T. Futatsugi et al, Fujitsu, 1998.
74. 2002/12-11 工研院電子所 半導體元件技術組/先進元件技術部 奈米電子計劃簡介 鍾朝安
75. J. B. Kim, D. R. Kwon, K. Chakrabarti, and Chongmu Lee, K. Y. Oh, J. H. Lee, “Improvement in Al2O3 dielectric behavior by using ozone as an oxidant for the atomic layer deposition technique”, J. Appl. Phys. 92, 2002.
76. 化學氣相沉積二氧化鋯閘極介電薄膜的結構與電性之研究,清華大學博士論文,黃世賢博士
77. 奈米級金粒子型單電子電晶體研發現況,胡淑芬,吳永俊.黃調元,劉如熹,葉儒林
78. E. H. Nicollian and A. Goetzberger, Bell Syst. Tech. J. 46, 1005 (1967).
79. S. Huang, S. Banerjee, R. T. Tung, and S. Oda, ”electron trapping, storing, and emission in nanocrystalline Si dots by capacitance-voltage and conductance-voltage measurement”, J. Appl. Phys. 93, 576 (2003).
80. M. Dai, K. Chen, X. Huang, L. Wu, L. Zhang, F. Qiao, W. Li, and K. Chen, ”Formation and charging effect of Si nanocrystals in a-SiNz/a-Si/a-SiNx structures”, J. Appl. Phys, 95, 640 (2004).
81. D. N. Kouvatsos, V. Ioannou-Sougleridis, A. G. Nassiopoulou, “Charging effects in silicon nanocrystals embedded in SiO2 films”, Materials science and Engineering B101, 270 (2003).
82. S. Saha and S. B. Krupanidhi, “Large reduction of leakage current by graded-layer La doping in (Ba0.5, Sr0.5)TiO3 thin films”, Appl. Phys. Lett. 79, 111 (2001).
83. Hong-Wen Wang, Siu-Wei Nien, and Kuok-Chuan Lee, “Enhanced tenability and electrical properties of barium strontium titanate thin films by gold doping in grains”, Appl. Phys. Lett. 84, 2874 (2004).