ITRS（International Technology Roadmap For Semiconductor）2003及2004指出當DRAM進入Mega-bit的集積度後，可利用Si3N4/SiO2（ONO）做為介電薄膜材料，再加上三度空間電容形狀的設計（Trench或Stack結構），可讓DRAM中每個Cell都能維持足夠的電容值以避免雜訊對0、1訊號的誤判。但當線寬尺度進入0.13微米以下，利用ONO做為介電薄膜來維持Cell足夠的電容值將愈來愈困難，因此採用新式的高介電薄膜材料將會是0.13微米以下的重點。本論文實驗將針對Al2O3高介電薄膜做為研究，利用其良好的化學穩定性和熱穩定性，研究做為DRAM電容材料的材料結構及電性上的探討。
此外在過去本實驗室曾對DRAM電容的上、下電極做過深入的探討，其中發現以含氧氣氛濺鍍出之PtOx薄膜發現具有增加電極表面積的效果。將所濺鍍之PtOx經由約300℃左右的熱處理溫度將使PtOx薄膜中的O脫離膜表面，使PtOx還原為Pt，且受到表面張力的影響，Pt將在膜表面收縮形成類似Si半球型晶粒的表面，將有效增加電極的接觸面積，達到增加電容值的效果。由此可知對於未來逐漸邁入奈米尺度的DRAM製程中，PtOx將會是深具潛力的電極材料。
除了PtOx電極材料的選擇外，近幾年另一項深具潛力的電極材料TiN也是近幾年研究重點。TiN原本在半導體工業中主要是當作防擴散的阻擋層來使用，主要是因為當元件速度上的要求愈來愈快，利用導電度較佳的Cu作為導電材料慢慢已成為趨勢，但Cu在升高溫熱處理的過程中擴散情況嚴重，為避免因擴散造成元件短路操作的問題，都會在鍍上Cu之前先在界面利用濺鍍或蒸鍍的方式鍍上一層TiN來阻擋擴散問題。因此在DRAM工業中若能直接以TiN做為導電的電極，不僅能有良好的製程整合性，對於將來採用MIM結構的DRAM電容也能簡化製程的步驟，降低成本。
因此本論文實驗當中將研究利用ALCVD做為成長Al2O3高介電常數材料，採用三甲基鋁 (trimethylaluminum, TMA) 作為Al的先趨物，水為氧化劑來進行Al2O3超微薄膜之鍍製。針對未來MIM電容結構中不同上、下電極對k值的影響。主要使用的底電極包括：Pt、PtOx、TiN三種不同形態表面k值的比較，並採用兩種不同上電極：Al、Au。同時也將做不同熱處理溫度對底電極表面粗糙度和對Al2O3電性上的影響。期望能把薄膜厚度控制在~10nm以下，獲得100奈米世代以下電容值的要求，漏電流控制在1V工作電壓下小於1x10-8 A/cm2。

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