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研究生： 柯昶丞
Ko, Chang-Cheng
論文名稱： 以節點增加與移除之方法來進行多數閘邏輯電路優化之 研究
Majority Logic Circuit Minimization Using Node Addition and Removal
指導教授： 王俊堯
Wang, Chun-Yao
口試委員: 黃俊達
Huang, Juinn-Dar
吳凱強
Wu, Kai-Chiang
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 資訊工程學系
Computer Science
論文出版年： 2020
畢業學年度： 108
語文別： 英文
論文頁數： 39
中文關鍵詞： 多數閘邏輯 、節點合併 、節點增加與移除 、邏輯優化
外文關鍵詞： majority logic, node-merging, node addition and removal, logic optimization
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    • 量子點細胞自動機由於其低功耗等特性而被認為是一種有潛力的新興科技。由於多數函式是量子點細胞自動機電路中的主要的運作方式，因此優化量子點細胞自動機電路中多數閘的數量對於優化量子點細胞自動機電路而言至關重要。先前的一項研究是使用節點合併技術在多數閘邏輯電路中將一個目標節點以現有存在在電路上的替代節點替換，以進行優化。但是當目標節點不存在替代節點時，此技術可能會失敗。在此研究中，我們為多數閘邏輯電路提出了一種增強的優化技術，方法是在電路中添加一個新節點，然後刪除目標節點及其扇入節點。實驗在EPFL基準電路集後，結果顯示該技術改進了節點合併技術的結果。此外，此技術可以與其他優化技術一起整合使用。與僅使用節點合併技術的電路相比，採用整合方法的電路大小減少了1.26倍。

    Quantum-dot Cellular Automata (QCA) is considered as a promising emerging technology due to its low power dissipation and high device density. Since the majority function is the main operation in QCA circuits, minimizing the number of majority gates in QCA circuits is crucial to the corresponding QCA circuit minimization. A previous work used the node-merging technique to replace one target node with an existing substitute node in majority circuits for optimization. However, this technique may fail when no substitute nodes exist for a target node. In this paper, we propose an enhanced optimization technique for majority circuits by adding a new node into the circuits and removing the target node and its fanin nodes. The experimental results show that this technique improves the results of the node-merging technique on a set of EPFL logic synthesis benchmarks. Additionally, this enhanced technique can work together with other optimization techniques. The circuit size reduction in the integrated approach reaches 1.26 times as compared to the results using node-merging technique.

    中文摘要i Abstract ii 誌謝辭iii Contents iv List of Tables vi List of Figures vii 1 Introduction 1 2 Preliminaries 5 2.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2 MA Computation for Majority Circuits . . . . . . . . . . . . . . . . . 7 2.3 Node-merging Approach . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.4 NAR Approach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 The Proposed Node Addition and Removal Approach for Majority Circuits 12 3.1 Sucient Conditions in NAR for Majority Circuits . . . . . . . . . . 12 3.2 Di erent Types of the Added Substitute Nodes . . . . . . . . . . . . 15 3.3 NAR Algorithm for Majority Circuits . . . . . . . . . . . . . . . . . . 15 4 MA reuse and Circuit Size Reduction for Majority Circuits 18 4.1 MA Reuse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.2 Circuit Size Reduction for Majority Circuits . . . . . . . . . . . . . . 20 4.2.1 Redundancy Removal . . . . . . . . . . . . . . . . . . . . . . . 20 4.2.2 Node-merging . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.2.3 Overall Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.2.4 Time Complexity of the Overall Algorithm . . . . . . . . . . . 21 5 Experimental Results 23 5.1 Replaceable Node Identi cation . . . . . . . . . . . . . . . . . . . . . 24 5.2 Circuit Size Reduction . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6 Conclusion 33 7 Acknowledgement 34 Bibliography 35

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