鍺相較於矽而言，電子的遷移率可提升兩倍、電洞的遷移率可以提升至四倍，故利用鍺材料在SOI FinFET上，達成更高的載子遷移率，以及high-k材料來達成超薄等效氧化層厚度，對於閘極漏電可以大大改善。
本論文的研究以使用於NDL實驗室內之UHV-CME、ASM四族磊晶機台（EPSILON 2000+)磊出單層或矽鍺超晶格虛擬基板，之後在基板上用ALD沉積HfO2作為介電層。
第一部分，使用磊晶成長方式在bulk FinFET電晶體之上，發現在SiGe+cap通道上，在電性上都表現的較SiGe還要突出，推測有一層Si cap在其之上，會使得鍺不易擴散至介面；此外，發現以矽鍺超晶格通道(2 Periods SiGe/Si)的效果在Ion/Ioff ratio、汲極電流、Gm、mobility的效果，皆明顯優於以矽鍺為通道之元件，並改善可靠度特性，因為在矽鍺之中插入一層類似矽阻擋層提升應力、減少鍺的updiffusion的現象。
第二部分，與前一章節差別於本章節先製作出SOI基板及鰭式電晶體的結構，再使用UHV-CME以包覆性的磊晶方式在通道上面，單層或週期性堆疊矽鍺虛擬基板。實驗結果可以發現，經過超晶格磊晶之後的FinFET較純矽或單層SiGe FinFET結構有更好的電特性，如較高的汲極電流、轉導值以及載子遷移率的提升，且S.S.(Subthreshold Swing)特性比單層SiGe還要好，猜測是因為在矽鍺之中插入一層類似矽阻擋層，提升應力及平整度。此外超晶格磊晶之Tinv達到2.05 nm，因為是過薄的矽覆蓋層，使得等效氧化層微縮上的困難。
第三部分，做矽鍺磊晶前經過高溫預烤去氧的影響探討，實驗結果發現，沒有經過高溫預烤之後可以壓低S.S.值、提高Gm值。從TEM圖認為高溫會使得表面較為不平整；此外，第三部分還有利用提升每一層矽鍺超晶格磊晶的厚度製作出SOI n-FinFET，探討其在電特性上的差異。實驗結果可以發現，提昇每一層矽鍺超晶格磊晶的厚度之後，得到較低的Tinv，並提升元件的驅動電流、載子遷移率，在Reliability特性上也有不錯的表現，推測因為Si cap增厚有助於阻擋Ge擴散至介面，而Ge的比例升高會有較多的載子在通道之內。

For germanium (Ge) material, it provides two times electron mobility and four times hole mobility than silicon (Si). Therefore, Ge is used as channel material in SOI FinFET to obtain high channel mobility. The interface between Ge and high-k dielectric is also investigated to obtain ultra-thin equivalent oxide thickness (EOT) and reduced gate leakage current.
Ultrahigh vacuum chemical molecular epitaxy (UHV-CME) and ASM (EPSILON 2000+), two facilities in National Nano Device Laboratories (NDL), are used to form SiGe and SiGe superlattice layers. Hafnium dioxide (HfO2) is deposited by Atomic Layer Deposition (ALD) as gate dielectric.
In the first part, Si/SiGe multi-layer is epitaxially grown layer-by-layer in Si bulk FinFET. For SiGe+cap, the electrical characteristics are better than SiGe, because SiGe+cap has Si cap to suppress Ge diffusion; The electrical characteristics of SiGe super lattice such as Ion/Ioff ratio, drain current, Gm, carrier mobility and subthreshold swing are improved. We predict that Si is added to SiGe layers can achieve higher strain effect and lower Ge up-diffusion.
In the second part, Si/SiGe multi-layer is successfully epitaxially grown on Si fin channel in SOI FinFET by using UHV-CME. Si/SiGe super lattice is helpful to obtain better electrical characteristics compared to SiGe+cap layer and control sample, such as drain current, Gm, carrier mobility and subthreshold swing are improved. We predict that Si is added to SiGe layers can achieve higher strain effect and improve interface. Furthermore, Si/SiGe super lattice achieve higher Tinv 2.05 nm. Because of the thinner Si cap, it is difficult to improve Tinv.
In the third part, in order to remove oxide on Si wafer, we use pre-baking 900℃ before SiGe+cap epitaxially grown on Si fin channel in SOI FinFET by using UHV-CME. For without pre-baking 900℃, the characteristics of subthreshold swing and Gm are better than pre-baking 900℃. From TEM, we consider that high temperature suffer from poor interfacial quality; In addition, the thickness of Si/SiGe super lattice is modulated in the third part. The electrical characteristics of SOI FinFETs with different Si/SiGe super lattice are discussed. For the thick Si/SiGe super lattice, the electrical characteristics are better than thinner Si/SiGe one. Higher saturation drain current and mobility, and lower Tinv are achieved by thick Si/SiGe super lattice. In addition, good reliability can be achieved as well. We predict that thick Si cap can suppress Ge diffusion and thick Ge layers have more carriers in the channel.

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