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研究生: 陳冠名
Kuan-Ming Chen
論文名稱: 應用於無線網路之寬頻低雜訊放大器及射頻前端電路之設計
Wideband Low-Noise Amplifier and RF Front-End Design for Wireless Applications
指導教授: 柏振球
Jenn-Chyou Bor
口試委員:
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年: 2007
畢業學年度: 96
語文別: 英文
論文頁數: 118
中文關鍵詞: 雜訊相消低雜訊放大器主動式相位分離器射頻前端電路寬頻
外文關鍵詞: noise canceling, LNA, active balun, RF front-end, wideband
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  • 這篇論文的主旨為設計一個在頻寬之內NF 都小於 3 dB 的低雜訊放大器並把它整合進射頻前端電路之中,其電路會把原本在晶片外的相位分離器整合至晶片中,以符合高度整合性的需求。為了達成雜訊小於3 dB的主旨,我們採用了雜訊相消技術到單端輸入和單端輸出的shunt-shunt feedback LNA之中。頻寬最佳化的低雜訊放大器在所要的頻寬 2.4 GHz 到6 GHz 中,其 NF 的表現皆在 3 dB之下。雜訊最佳化的低雜訊放大器在目標頻段 2.6 GHz 上有 NF 等於 1.05 dB 的表現。
    為了符合高度整合的要求,我們使用了寬頻主動式而不使用電感的相位分離器。此相位分離器可使原本單端的RF及LO輸入變成差動式訊號來供給其後的雙平衡吉伯式混頻器做使用。相位分離器的模擬結果為在所要的頻寬之內 (2.4 GHz到 6 GHz),其增益誤差小於0.75 dB,而相位誤差則小於1.55度。
    結合以上的子電路就可以形成兩個電路系統:頻寬最佳化以及雜訊最佳化的射頻前端電路。這兩個電路皆使用TSMC 0.18-μm 1P6M RFCMOS的製程。在2.4 GHz 到 6 GHz中,頻寬最佳化的射頻前端電路之量測結果為13.8 dB ~ 19.7 dB的增益和6 dB ~ 9.4 dB 的NFSSB 。在1.8 伏特的電壓下,其所耗的電流包含輸出緩衝器為27.2 mA。至於雜訊最佳化的射頻前端電路在2.6 GHz時的量測結果為21.5 dB的增益、4.58 dB的NFSSB。在1.8 伏特的電壓下,其所耗的電流包括輸出緩衝器為15.4 mA。


    The main goals of this thesis are to design a wideband low noise amplifier (LNA) with noise figure (NF) lower than 3 dB and integrate it into the RF front-end with on-chip baluns. In order to achieve the low NF requirement, the noise canceling technique is applied to the single-ended shunt-shunt feedback LNA. The simulated NF of bandwidth-optimized LNA is lower than 3dB over the interest bandwidth from 2.4 GHz to 6 GHz and that of the noise-optimized LNA is only 1.05 dB at the target frequency, 2.6 GHz.
    To meet the need of highly integration, wideband active balun without any inductor is adopted for the differential conversion of single-ended RF and LO signals. Therefore, the double-balanced Gilbert-cell mixer can be used after. Simulated results show that gain error and phase error of the active balun are less than 0.75 dB and 1.55 degree, respectively.
    By integrating above blocks, two RF front-end circuits are designed for bandwidth and noise optimization, respectively. The test chips are fabricated by TSMC 0.18-μm 1P6M RFCMOS process. For the bandwidth-optimized RF front-end, over the whole interest bandwidth, the measured conversion power gain is from 13.8 dB to 19.7 dB and NFSSB is from 6 dB to 9.4 dB. The current consumption including output buffer is 27.2 mA under 1.8 V VDD. For the noise-optimized RF front-end, the measured results at 2.6 GHz are 21.5 dB conversion power gain, 4.58 dB NFSSB, and 15.4mA current consumption (including output buffer) under 1.8 V VDD.

    Chapter 1 Introduction………………………………………………....1 1.1 Motivation………………………………………………………...1 1.2 System Overview…………………………………………………2 1.2.1 Overview of Wireless LAN Standards…………………………………...2 1.2.2 Receiver Architectures…………………………………………………...4 1.3 Thesis Organizations……………………………………………...8 Chapter 2 Wideband Low Noise Amplifier Design…………………...9 2.1 Introduction……………………………………………………….9 2.2 Broadband LNA topologies……………………………………….9 2.2.1 Resistor-Terminated Common-Source Amplifier…………………………9 2.2.2 Common-Gate Amplifier………………………………………………...10 2.2.3 Distributed LNA………………………………………………………....12 2.2.3 Chebyshev Filter-Type LNA……………………………………….........13 2.2.5 Shunt-Shunt Feedback LNA…………………………………………….15 2.3 Proposed Wideband LNA………………………………………..17 2.3.1 Circuit Topology………………………………………………………..17 2.3.2 Noise Canceling Technique…...……………….…….…….…………....20 2.3.3 Analysis of Proposed Wideband LNA……………………………….…27 2.3.4 Bandwidth-Optimized Design…………………………………………..33 2.3.5 Noise-Optimized Desgin………………………………………………..39 2.4 Simulation Results……………………………………………….42 2.5 Summary…………………………………………………………49 Chapter 3 Down-Conversion Mixer Design with Active Balun…….50 3.1 . Introduction……………………………………………………...50 3.2 Wideband Active Balun…………………………………………50 3.2.1 Circuit Topology………………………………………………………..50 3.2.2 Output Balance Analysis………………………………………………..52 3.3 Active Gilbert-Cell Mixer……………………………………….56 3.3.1 Circuit Topology………………………………………………………..56 3.3.2 Conversion Gain………………………………………………………...57 3.3.3 Switching Stage Analysis……………………………………………….58 3.3.4 Mixer Noise Analysis…………………………………………………...58 3.4 Simulation Results……………………………………………….60 3.5 Summary…………………………………………………………65 Chapter 4 RF Front-End Implementation and Chip Measurement Results .…66 4.1 2~6 GHz RF Front-End Integration…………………………...…66 4.1.1 Bandwidth-Optimized RF Front-End………………………………...…66 4.1.2 Noise-Optimized RF Front-End………………………………………...70 4.2 Chip Measurement Results………………………………………..74 4.2.1 Measurement Setup……………………………………………………..74 4.2.2 Bandwidth-Optimized Low Noise Amplifier…………………………...76 4.2.3 Bandwidth-Optimized RF Front-End………………………..………….82 4.2.4 Noise-Optimized RF Front-End……………………………………..….88 4.2.5 Measurement Discussion………………………………………………..94 4.3 Summary…………………………………………………..………98 Chapter 5 Conclusions and Future Works……………………...……99 BIBLOGRAPHY………………………………………………..……102

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