近十年來半導體產業的爆炸性發展，使得可攜帶的個人化電子裝置更加普及。為了滿足資料在失去電源供應後仍能保存的需求，非揮發性記憶體(Nonvolatile Memory, NVM)所扮演的角色愈趨重要。同時，非揮發性記憶體正逐漸朝向內嵌式的晶片發展，如此一來便能有效降低電路板的面積，使得電子產品更加輕薄、更具有競爭力。然而在90nm製程以後，在傳統非揮發性記憶體中占有主流地位的快閃記憶體遭受了製程微縮上的挑戰。原因包括閘極氧化層漏電流、極高的操作電壓、電容耦合與過大的面積等等，進而使其在發展上受限。且傳統的非揮發性記憶體元件並不相容於邏輯製程，繁瑣製程的步驟不但衝擊著良率與可靠度，更造成整合上的困難並使製造成本節節上升。
然而本篇論文則是提出另一種非揮發一次性寫入(One-Time Programmable, OTP)記憶體元件，其相容於一般的邏輯製程，不須增加額外的光罩。此元件是將兩個串聯電晶體的閘極互相靠近，使其本身的間隙壁(spacer)融合在一起，產生了自我對準的氮化矽(Self-Aligned Nitride, SAN)作為電荷之儲存區，稱之為SAN記憶體元件。元件採用源極注入機制(Source-Side Injection, SSI)作為寫入操作，並利用選擇閘極(Select Gate, SG)與寫入閘極(Program Gate, PG)控制。另外，可利用帶對帶熱電洞(Band-to-Band Hot Holes, BBHH)進行抹除操作以探討此OTP多次性寫入(Multi-Time Programmable, MTP)的可能性。
SAN記憶體元件符合低功率、製程簡易、面積小等優點，且因其是以氮化矽作為儲存的介質，與傳統的浮閘極快閃記憶體相比，閘極氧化層厚度的下降不會造成嚴重的漏電問題，因此在未來製程的微縮上具有很大的競爭優勢。

Semiconductor manufacturing technology has evolved drastically in past decades, resulting in the popularization of personal and portable electronic devices. Almost all electronic devices need Non-Volatile Memory (NVM) to meet storage requirement since important information need to be kept when power is cut off. Meanwhile, single NVM memory chip is converted into embedded NVM (eNVM) chip gradually. Hence, the area of circuits can be reduced efficiently, making electronic products lighter, thinner and more competitive. Nevertheless, Flash memory, which composes mainstream of NVM products, has confronted lots of challenges in 90nm technology and beyond, including gate oxide leakage, high operation voltage, capacitive coupling and oversized area. Besides, comparing to pure logic process, traditional NVM devices require a dozen of masks and additional process steps, which will rising costs, and leads to yield and reliability concerns.
However, this thesis has presented another novel One-Time Programmable (OTP) memory cell, fully compatible with CMOS logic process, thus it does not need any additional mask. This memory cell is fabricated by placing two series gates as close as possible. By doing so, Self-Aligned Nitride (SAN) is formed by the merged spacer of two series transistor, as charge storage node; therefore, it is named SAN memory cell. The SAN cell uses Source-Side Injection (SSI) as program mechanism, which is controlled by Program Gate (PG) and Select Gate (SG). Band-to-Band Hot Holes (BBHH) as erase mechanism are also discussed for the evaluation of Multi-Time Programmable (MTP) operation.
SAN memory cell has exhibited its excellent features of low power, simple process and small area. Moreover, since Silicon Nitride is used as storage material instead of Poly Silicon, the gate oxide thickness can be reduced further. This makes SAN memory cell be promising candidate in scaled technologies.

[1] Ching-Sung Yang, Shin-Jye Shen and Ching-Hsiang Hsu, “Single poly UV-erasable programmable read only memory,” US Patent # US 6882574 B2, Apr.19, 2005.
[2] Robert S.-C. Wang, Rick S.-J. Shen and Charles C.-H. Hsu, “Neobit® - high reliable logic non-volatile memory (NVM),” International Federation of Placenta Associations (IPFA), 2004, pp.111-114.
[3] Charles Ching-Hsiang Hsu, Yen-Tai Lin and Shin-Jye Shen, “Future prospective of programmable logic non-volatile device,” ASSCC 2006 IEEE Asian, Nov. 2006, pp.35-37.
[4] Jack Zezhong Peng, “Semiconductor memory cell and memory array using a breakdown phenomena in an ultra-thin dielectric,” US Patent # US 6667902 B2, Dec.23, 2003.
[5] Fong et al., “Programming methods and circuits for semiconductor memory cell and memory array using a breakdown phenomena in an ultrathin dielectric,” US Patent # US 6671040 B2, Dec.30, 2003.
[6] Peng, G .Rosendale, M. Fliesler, D. Fong, J. Wang, C. Ng, Zs Liu and Harry Luan, “A novel embedded OTP NVM using standard foundry CMOS logic technology,” IEEE Non-Volatile Semiconductor Memory Workshop, Feb 2006.
[7] C. Kothandaraman, Sundar K. Iyer, and Subramanian S. Iyer, “Electrically programmable fuse (eFUSE) using electromigration in Silicides,” IEEE Electron Device Letter, vol. 23, no. 9, Sep 2002, pp. 523-525.
[8] Johannes Fellner, “A one time programming cell using more than two resistance levels of a polyfuse,” IEEE Custom Integrated Circuits Conference, Sep 2005, pp. 263-266.
[9] J. Safran, et al., “A compact eFUSE programmable array memory for SOI CMOS,” Sympposium on VLSI Circuits Digest of Technical Papers, Jun 2007, pp. 72-73.
[10] Jan De Blauwe, et al., “SILC-related effects in flash E2PROM’s—part I: a quantitative model for steady-state SILC,” IEEE Transections on Electron Devices, vol. 45, no. 8, Aug 1998, pp. 1745-1750.
[11] Jan De Blauwe, et al., “SILC-related effects in flash E2PROM’s—part II: prediction of steady-state SILC-related disturb characteristics,” IEEE Transections on Electron Devices, vol. 45, no. 8, Aug 1998, pp. 1751-1760.
[12] Chien-Sheng Hsieh, et al., “NVM characteristics of single- MOSFET cells using Nitride spacers with gate-to-drain NOI,” IEEE Transections on Electron Devices, vol. 51, no. 11, Nov 2004, pp. 1811-1817.
[13] Erik S. Jeng, et al., “Investigation of programming charge distribution in nonoverlapped implantation nMOSFETs,” IEEE Transections on Electron Devices, vol. 53, no. 10, Oct 2006, pp. 2517-2524.
[14] Erik S. Jeng, et al., “Performance improvement and scalability of nonoverlapped implantation nMOSFETs with charge-trapping spacers as nonvolatile memories,” IEEE Transections on Electron Devices, vol. 54, no. 12, Dec 2007, pp. 3299-3307.
[15] Shiu-Ko Jangiian, Szu-An Wu and Sheng-Wen Chen, “Metal gate structure of a semiconductor device,” US Patent # US 8294202 B2, Dec.23, 2012.
[16] Dick James, “High-kmetal gates in leading edge silicon devices,” IEEE Advanced Semiconductor Manufacturing Conference (ASMC), May 2012, pp. 346-353.
[17] T. H. Ning, “Hot-electron emission from silicon into silicon dioxide,” Solid-State Electronics, vol. 21, 1978, pp. 273-282.
[18] Chenming Hu, “Lucky-electron model of channel hot electron emission,” IEEE International Electron Devices Meeting, Dec. 1979, pp. 22-25.
[19] Simon Tam, P.-K. Ko and Chenming Hu, “Lucky-electron model of channel hot-electron injection in MOSFET’s,” IEEE Transections on Electron Devices, vol. 31, no. 9, Sep 1984, pp. 1116-1125.
[20] Richard B. Fair and Robert C. Sun, “Threshold voltage instability in MOSFET's due to channel hot hole emission,” IEEE Transections on Electron Devices, vol. 28, no. 1, Jan 1981, pp. 83-94.
[21] Paolo Pavan, Roberto Bez, Piero Olivo and Enrico Zanoni, “Flash memory cells-an overview,” Proceedings of the IEEE, vol. 85, no. 8, Aug 1907, pp. 1248-1271.
[22] A.-T. Wu, T.-Y. Chan, P.-K. Ko and Chemming Hu, “A novel high-speed, 5-volt programming EPROM structure with source-side injection,” IEEE International Electron Devices Meeting, Dec. 1986, pp. 584-587.
[23] A.-T. Wu, T.-Y. Chan, P.-K. Ko and Chemming Hu, “A source-side injection erasable programmable read-only-memory (SI-EPROM) device,” IEEE Electron Device Letters, vol. 7, no. 9, Sep 1986, pp. 540-542.
[24] Jan Van Houdt, Paul Heremans, Ludo Deferm, Guido Groeseneken, and Herman E. Maes, “Analysis of the enhanced hot-electron injection in split-gate transistors useful for EEPROM applications,” IEEE Transections on Electron Devices, vol. 39, no. 5, May 1992, pp. 1150-1156.
[25] Jan Van Houdt, Luc Haspeslagh, Dirk Wellekens, Ludo Deferm, Guido Groeseneken, and Herman E. Maes, “HIMOS-a high efficiency flash E2PROM cell for embedded memory applications,” IEEE Transections on Electron Devices, vol. 40, no. 12, Dec 1993, pp. 2255-2263.
[26] Chi Chang, Sameer Haddad, Balaji Swaminathan and Jih Lien, “Drain-avalanche and hole-trapping induced gate leakage in thin-oxide MOS devices,” IEEE Electron Device Letters, vol. 9, no. 11, Nov 1988, pp. 588-590.
[27] K. Kurimoto, Y. Odake and S. Odanaka, “Drain leakage current characteristics due to the band-to-band tunneling in LDD MOS devices” IEEE International Electron Devices Meeting, Dec. 1989, pp. 621-624.
[28] Ih-Chin Chen, D. J. Coleman and C. W. Teng, “Gate current injection initiated by electron band-to-band tunneling in MOS devices,” IEEE Electron Device Letters, vol. 10, no. 7, Jul 1989, pp. 297-300.
[29] Yasuo Igura, Hideyuki Matsuoka and E. Takeda, “New device degradation due to 'cold' carriers created by band-to-band tunneling,” IEEE Electron Device Letters, vol. 10, no. 5, May 1989, pp. 227-229.
[30] Joe E. Brewer, Manzur Gill, Nonvolatile Memory Technologies with Emphasis on Flash, IEEE press, 2008
[31] Adam Brand, Ken Wu, Sam Pan and David Chin, “Novel read disturb failure mechanism induced by FLASH cycling,” IEEE Reliability Physics Symposium, Mar 1993, pp. 127-132.
[32] J. D. Plummer, M. D. Deal and P. B. Griffin, Silicon VLSI Technology Fundamentals, Practice Modeling, Prentice-Hall, 2000.
[33] Dieter K. Schroder, Semiconductor Material and Device Characterization, Wiley, 2006.
[34] E. H. Nicollian, J. R. Brews, MOS (Metal Oxide Semiconductor) Physics and Technology, Wiley, 2002.
[35] E. H. Snow, A.S. Grove, B. E. Deal and C. T. Sah, “Ion transport phenomena in insulating films,” Journal of Applied Physics, vol. 36, no. 5, May 1963, pp. 1664-1673.
[36] E. I. Goldman, A. G. Zhdan and G. V. Chucheva, “Ion transport phenomena in oxide layer on the silicon surface,” Journal of Applied Physics, vol. 89, no. 1, Jan 2001, pp. 130-145.
[37] E. A. Fogels and C. A. T. Salama, “Characterization of surface states at the Si-SiO2 interface,” Journal of The Electrochemical Society, vol. 118, no. 12, Dec 1971, pp. 2002-2006.
[38] J.S. Brugler and P.G.A. Jespers, “Charge pumping in MOS devices,” IEEE Transections on Electron Devices, vol. ED-16, no. 3, Mar 1969, pp. 297-302.
[39] Guido Groeseneken, Herman E. Maes, Nicolas Beltran and Roger F. De Keersmaecker, “A reliable approach to charge-pumping measurements in MOS transistors,” IEEE Transections on Electron Devices, vol. ED-31, no. 1, Jan 1984, pp. 42-53.
[40] Y. Liang, W. Zhao, M. Z. Xu and C. H. Tan, “A new charge-pumping measurement technique for lateral profiling of interface states and oxide charges in MOSFETs,” IEEE Solid-State and Integrated-Circuit Technology, Oct 2001, pp. 982-985.
[41] Yu-lin Chu, Da-Wen Lin and Ching-Yuan Wu, “A new charge-pumping technique for profiling the interface-states and oxide-trapped charges in MOSFETs,” IEEE Transections on Electron Devices, vol. 47, no. 2, Feb 2000, pp. 348-353.
[42] Masakatsu Tsuchiaki, Hisashi Hara, Toyota Morimoto and Hiroshi Iwai, “A new charge pumping method for determining the spatial distribution of hot-carrier-induced fixed charge in p-MOSFETs,” IEEE Transections on Electron Devices, vol. 40, no. 10, Oct 1993, pp. 1768-1779.
[43] Han-Chao Lai, Kai-Yuan Cheng, Ya-Chin King and Chrong-Jung Lin, “A 0.26-µm2 U-Shaped nitride-based programming cell on pure 90-nm CMOS technology,” IEEE Electron Device Letters, vol. 29, no. 9, Sep 2007, pp. 837-839.
[44] Ying-Je Chen, Chia-En Huang, Hsin-Ming Chen, Han-Chao Lai, J. R. Shih, Kenneth Wu, Ya-Chin King and Chrong-Jung Lin, “A novel 2-bit/cell p-channel logic programmable cell with pure 90-nm CMOS technology,” IEEE Electron Device Letters, vol. 29, no. 8, Aug 2008, pp. 938-940.
[45] Han-Chao Lai, Chia-En Huang, Ya-Chin King, and Chrong-Jung Lin, “Novel self-aligned nitride one time programming with 2-bit/cell based on pure 90-nm complementary metal–oxide–semiconductor logic technology,” Japanese Journal of Applied Physics, vol. 47, no. 11, Aug 2008, pp. 8369–8374.
[46] Chia-En Huang, Ying-Je Chen, Hsun OuYang, Chrong-Jung Lin and Ya-Chin King, “Source side injection programmed p-channel self-aligned-nitride one-time programming cell for 90 nm Logic nonvolatile memory applications,” Japanese Journal of Applied Physics, vol. 49, no. 4, 2010.
[47] Chia-En Huang, ilsin-Ming Chen, Han-Chao Lai, Ying-Je Chen, Ya-Chin King and Chrong Jung Lin, “A new self-aligned nitride MTP cell with 45nm CMOS fully compatible process,” IEEE International Electron Devices Meeting, Dec. 2007, pp. 91-94.
[48] Chia-En Huang, Ying-Je Chen, Han-Chao Lai, Ya-Chin King and Chrong Jung Lin, “A study of self-aligned nitride erasable OTP cell by 45-nm CMOS fully compatible process,” IEEE Transections on Electron Devices, vol. 56, no. 6, Jun 2009, pp. 1228-1234.
[49] Wen Chao Shen, Chia-En Huang, Hsun OuYang, Ya-Chin King, and Chrong Jung Lin, “32nm strained nitride MTP cell by fully CMOS logic compatible process,” International Symposium on VLSI Technology, Systems, and Applications, Apr 2012, pp. 1-2.