為了要建立一個準確的分離閘快閃記憶體之資料保存模型，我們首先建立了一個經由讀取電流特性來淬取浮動閘極電位的方法論。在過去的許多研究中指出，由於寫入與抹除的過程會造成氧化層的退化與漏電流的產生，導致快閃記憶體的資料保存生命週期因此縮短。我們考慮了電荷保存定律與缺陷輔助穿透漏電流，分離閘快閃記憶體在低溫烘烤下的資料流失特性就可以準確的被模型化。此外，資料保存生命週期會隨著寫入抹除次數上升而有所退化，這項特性也可以同時被觀察到。
另外，為了發展一個更有效率的資料保存測試方法，我們利用電壓加速的方式取代了傳統利用高溫加速的方式。我們採用了不同的字線電壓來加速資料流失的過程，並藉由外加電壓與資料保存生命週期的關連性，找到了一般操作條件下的資料保存生命週期。因為電壓加速的效率非常高，這樣的方式除了有效的縮短了測試時間，同時仍然可以準確的預測正常操作條件下，快閃記憶體的資料保存特性。
利用前述發展出來的可靠度模型，我們針對不同溫度下的可靠度分析、生命週期與閘極氧化層厚度間的關係、生命週期與元件面積間的關係，逐一的深入加以討論。我們的研究成果指出，對於高可靠度的快閃記憶體產品而言，若要達成十五年的生命週期內，只有百萬分之一的失效率，就必須採用厚度是10奈米以上的閘極氧化層

In developing an accurate lifetime prediction model for post-cycling data retention failure rate of split-gate flash memories, a floating-gate potential extraction method from the measured bit-cell-current data is proposed. Stress induced leakage current through the coupling oxide caused by source side channel hot electron injection during program operation is the major cause for post-cycling data retention failure bits. Considering charge conservation and trap-assist-tunnelling (TAT) leakage current, the charge gain behavior under low temperature bake is modelled and the failure rate under various measured conditions can be predicted precisely. We have found that data retention lifetime decrease as P/E cycling increases, while failing bits increase with numbers of P/E cycling.
In addition, in order to develop a fast statistical testing methodology to predict post-cycling low-temperature-data-retention (LTDR) lifetime of split-gate flash memories, word-line stress is used to accelerate the charge gain effect responsible for bit-cell-current (BCC) reduction among the tail-bits. To find out the voltage dependence on data retention lifetime, various word-line stress voltages are performed to enhance the charge gain effect of the erased-state cells. At an accelerated state, word-line stress lifetime tests can be completed within a much shorter test period and still provide accurate lifetime prediction for embedded flash memory products.
Based on the reliability statistics and TAT-related lifetime model introduced in chapter three, the thermal-acceleration reliability statistics, gate-oxide thickness dependence, and device area (cells per array/chip) dependence on data-retention lifetime of high-reliability flash memory products are comprehensively discussed. According to the gate-oxide dependence on data-retention lifetime, a gate-oxide thickness of 10nm is required to achieve a single-ppm parts-level failure rate in fifteen years for high-reliability flash memory products.

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